Stress reduction package and process

Claim 1

An integrated circuit package, which comprises a die attach pad, a stress reduction pad attached to said die attach pad, said stress reduction pad having a coefficient of thermal expansion equal to or approximately matching the coefficient of thermal expansion of silicon, a silicon integrated circuit die attached to a surface of said stress reduction pad facing away from said metal die attach pad, the surface having a portion extending beyond each side of said integrated circuit die, and an encapsulating body of thermosetting resin around said die attach pad, said stress reduction pad and said integrated circuit die, said thermosetting resin adhering to the surface portion to produce an enhanced stress reduction, said stress reduction pad having vertical edges extending above said die attach pad proximate to vertical edges of the integrated circuit die, said vertical edges of said stress reduction pad resisting forces applied by said thermosetting resin to said vertical edges of the stress reduction pad and to said integrated circuit die to reduce stress applied by said thermosetting resin to said integrated circuit die, said integrated circuit die being symmetrically placed on said stress reduction pad and said stress reduction pad having a width of about (x+y)/2, where x is a width of said integrated circuit die and y is a width of said die attach pad.