US5049836A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High voltage electrical amplifier having a short rise time
Assignee: United States Department of Energy
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Filing: 1989-12-07
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Granted: 1991-09-17
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Expires: 2009-12-07
Abstract
Abstract A circuit, comprising an amplifier and a transformer is disclosed that produces a high power pulse having a fast response time, and that responds to a digital control signal applied through a digital-to-analog converter. The present invention is suitable for driving a component such as an electro-optic modulator with a voltage in the kilovolt range. The circuit is stable at high frequencies and during pulse transients, and its impedance matching circuit matches the load impedance with the output impedance. The preferred embodiment comprises an input stage compatible with high-speed semiconductor components for amplifying the voltage of the input control signal, a buffer for isolating the input stage from the output stage; and a plurality of current amplifiers connected to the buffer. Each current amplifier is connected to a field effect transistor (FET), which switches a high voltage power supply to a transformer which then provides an output terminal for driving a load. The transformer comprises a plurality of transmission lines connected to the FETs and the load. The transformer changes the impedance and voltage of the output. The preferred embodiment also comprises a low voltage power supply for biasing the FETs at or near an operational voltage.
Inventors
- 👤 David J. Christie
- 👤 Gregory E. Dallum
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:07
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/20; H03F3/21; H03F3/217; H03F3/2178; H03F3/211; H03F3/2171; H03F3/50; H03F2200/00; H03F2200/387; H03F2200/541
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
269 words
An electrical circuit for providing a high voltage output across a first terminal and a second terminal, the output being responsive to a low voltage control input, said electrical circuit comprising: an amplifier circuit coupled to the low voltage control input, said amplifier circuit comprising, an input stage coupled to the low voltage input, a current amplifier coupled to the input section, and a FET connected to the current amplifier, said amplifier circuit having an output provided across a first line and a second line; and, an impedance transformer coupled to the output of the amplifier, said transformer comprising a plurality of transmission lines including a first transmission line, at least one intermediate transmission line, and a final transmission line, each transmission line comprising, an input including a first input line coupled to the first line of the amplifier output, and a second input line coupled to the second line of the amplifier output, and an output including a first output line and a second output line, wherein the first output line of the first transmission line is connected to the first terminal, the second output of the first transmission line is connected to the first output of the subsequent transmission line, the second output of the subsequent transmission line is connected to the first output of the next subsequent transmission line, and so forth in repeating fashion for each successive transmission line until in the final transmission line, the second output line of the final transmission line is connected to the second terminal, so that a high voltage output is provided across the first and the second terminals.
Claim 2
Dependent Claim
269 words
An electrical circuit for providing a high voltage output across a first terminal and a second terminal, the output being responsive to a low voltage control input, said electrical circuit comprising: an amplifier circuit coupled to the low voltage control input, said amplifier circuit comprising, an input stage coupled to the low voltage input, a current amplifier coupled to the input section, and a FET connected to the current amplifier, said amplifier circuit having an output provided across a first line and a second line; and, an impedance transformer coupled to the output of the amplifier, said transformer comprising a plurality of transmission lines including a first transmission line, at least one intermediate transmission line, and a final transmission line, each transmission line comprising, an input including a first input line coupled to the first line of the amplifier output, and a second input line coupled to the second line of the amplifier output, and an output including a first output line and a second output line, wherein the first output line of the first transmission line is connected to the first terminal, the second output of the first transmission line is connected to the first output of the subsequent transmission line, the second output of the subsequent transmission line is connected to the first output of the next subsequent transmission line, and so forth in repeating fashion for each successive transmission line until in the final transmission line, the second output line of the final transmission line is connected to the second terminal, so that a high voltage output is provided across the first and the second terminals.
Claim 3
Dependent Claim
25 words
The electrical circuit as claimed in claim 1, wherein the current amplifier comprises at least one bipolar high speed transistor connected in a Darlington configuration.
Claim 4
Dependent Claim
43 words
The electrical circuit as claimed in claim 1, further comprising a means for biasing the FET, said biasing means including a DC voltage source connected to the input stage, said voltage source being coupled through the circuit to the gate of the FET.
Claim 5
Dependent Claim
35 words
The electrical circuit as claimed in claim 3, further comprising a number of ferrite cores equalling the number of transmission lines, wherein a length of each transmission line is wrapped around its corresponding ferrite core.
Claim 6
Dependent Claim
37 words
The electrical circuit as claimed in claim 1, further comprising a resistor capacitively coupled between the gate and source of the FET, whereby the adjacent current amplifier stage is limited in gain, and circuit stability is enhanced.
Claim 7
Dependent Claim
36 words
The electrical circuit as claimed in claim 1, further comprising an electro-optic crystal coupled to the first terminal and the second terminal, so that the output of the electrical circuit is applied across the electro-optic crystal.
Claim 8
Dependent Claim
153 words
An electrical circuit for providing a high voltage output across a first terminal and a second terminal, said high voltage output being responsive to a low voltage control input, said electrical circuit comprising: an amplifier circuit coupled to the control input, said circuit including a current amplifier; an input stage and a buffer coupling the control input and the amplifier circuit, a FET coupled to the current amplifier, said FET providing an output across its drain and source; means for biasing the FET into its approximately linear mode of operation, so that the FET operates in a substantially linear mode during a rising portion of the input waveform, said biasing means including a DC voltage source connected to the input stage, said voltage source being coupled through the circuit to the gate of the FET; and, a transformer coupled to the output of the FET, said transformer comprising a plurality of transmission lines.
Claim 9
Dependent Claim
153 words
An electrical circuit for providing a high voltage output across a first terminal and a second terminal, said high voltage output being responsive to a low voltage control input, said electrical circuit comprising: an amplifier circuit coupled to the control input, said circuit including a current amplifier; an input stage and a buffer coupling the control input and the amplifier circuit, a FET coupled to the current amplifier, said FET providing an output across its drain and source; means for biasing the FET into its approximately linear mode of operation, so that the FET operates in a substantially linear mode during a rising portion of the input waveform, said biasing means including a DC voltage source connected to the input stage, said voltage source being coupled through the circuit to the gate of the FET; and, a transformer coupled to the output of the FET, said transformer comprising a plurality of transmission lines.
Claim 10
Dependent Claim
42 words
The electrical circuit as claimed in claim 7, further comprising a resistor capacitively coupled between the gate and source of the FET, whereby the current amplifier stage preceding the FET is limited in gain by the resistor, and circuit stability is enhanced.
Claim 11
Dependent Claim
195 words
The electrical circuit as claimed in claim 8, wherein said transformer comprises a plurality of transmission lines including a first transmission line, at least one intermediate transmission line, and a final transmission line, each transmission line comprising, an input including a first input line coupled to the drain of the FET, and a second input line coupled to the source of the FET, an output including a first output line and a second output line, wherein the first output line of the first transmission line is connected to the first terminal, the second output of the first transmission line is connected to the first output of the subsequent transmission line, the second output of the subsequent transmission line is connected to the first output of the next subsequent transmission line, and so forth in repeating fashion for each successive transmission line until in the final transmission line, the second output line of the final transmission line is connected to the second terminal, so that a high voltage output is provided across the first and the second terminals, with the output impedance being determined in part by the number of transmission lines and their individual impedance.
Claim 12
Dependent Claim
35 words
The electrical circuit as claimed in claim 9, further comprising a number of ferrite cores equalling the number of transmission lines, wherein a length of each transmission line is wrapped around its corresponding ferrite core.
Claim 13
Dependent Claim
35 words
The electrical circuit as claimed in claim 10, wherein the number of transmission lines is five, and the transmission lines each have an impedance of approximately 10Ω, thus providing an output impedance of approximately 50Ω.
Claim 14
Dependent Claim
21 words
The electrical circuit as claimed in claim 9, further comprising at least one FET connected in parallel with the first FET.
Claim 15
Dependent Claim
16 words
The electrical circuit as claimed in claim 12, wherein the total number of FETs is five.
Claim 16
Dependent Claim
26 words
The electrical circuit as claimed in claim 7, wherein the current amplifier comprises at least one bipolar microwave pulsed power transistor connected in a Darlington configuration.
Claim 17
Dependent Claim
42 words
The electrical circuit as claimed in claim 14 further comprising a resistor capacitively coupled between the gate and source of the FET, whereby the current amplifier stage preceding the FET is limited in gain by the resistor, and circuit stability is enhanced.
Claim 18
Dependent Claim
37 words
The electrical circuit as claimed in claim 15, further comprising a high voltage power supply having a terminal coupled to the drain of the FET and an opposite polarity terminal coupled to the source of the FET.
Claim 19
Dependent Claim
123 words
An electrical circuit for providing a pulse in response to an input control signal, said circuit comprising: an input stage comprising a means for amplifying the voltage of the input control signal; a buffer connected to the input stage; a current amplifier connected to the buffer, said current amplifier having an output voltage responsive to the voltage of the input control signal, a FET coupled to the output of the current amplifier; means for biasing the FET into its approximately linear mode of operation, so that the FET operates in a substantially linear mode during a rising portion of the input waveform; and a transmission line transformer coupled to the output of the FET, said transformer having an impedance that is substantially resistive.
Claim 20
Dependent Claim
123 words
An electrical circuit for providing a pulse in response to an input control signal, said circuit comprising: an input stage comprising a means for amplifying the voltage of the input control signal; a buffer connected to the input stage; a current amplifier connected to the buffer, said current amplifier having an output voltage responsive to the voltage of the input control signal, a FET coupled to the output of the current amplifier; means for biasing the FET into its approximately linear mode of operation, so that the FET operates in a substantially linear mode during a rising portion of the input waveform; and a transmission line transformer coupled to the output of the FET, said transformer having an impedance that is substantially resistive.
Claim 21
Dependent Claim
22 words
The electrical circuit as claimed in claim 17, wherein the current amplifier comprises a plurality of bipolar transistors in a Darlington configuration.
Claim 22
Dependent Claim
17 words
The electrical circuit as claimed in claim 18 wherein the bipolar transistors comprise a pulsed power transistor.
Claim 23
Dependent Claim
49 words
The electrical circuit as claimed in claim 17, comprising a plurality of current amplifiers and an equal number of FETs, the input of each current amplifier being coupled to the buffer, the output of each current amplifier being coupled to, and associated with, the input of a respective FET.
Claim 24
Dependent Claim
36 words
The electrical circuit as claimed in claim 20, wherein the biasing means includes a DC voltage source connected to the input stage, said voltage source being coupled through the circuit to the gate of each FET.
Claim 25
Dependent Claim
55 words
The electrical circuit as claimed in claim 21, further comprising a plurality of resistors connected to the plurality of FETs, each resistor being capacitively coupled between the gate and source of a respective FET, whereby the current amplifier stage preceding each FET is limited in gain by the respective resistor, and circuit stability is enhanced.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-16 | 1995-03-18 | 1995-09-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-16 | 1999-03-18 | 1999-09-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-16 | 2003-03-18 | 2003-09-17 | $7700.00 | Window Closed / Lapsed |