Semiconductor memory device having buried structure to suppress soft errors

Claim 2

A semiconductor memory device comprising: a semiconductor substrate of a certain conductivity type having a main surface, with said substrate having a prescribed impurity concentration for said certain conductivity type; a charge storage capacitor and a write/read transistor having a gate formed on said main surface; and a continuous buried layer formed in said substrate having an impurity concentration higher than that in said substrate for said certain conductivity type, wherein said buried layer is formed at a first depth beneath the capacitor and at a second depth greater than the first depth beneath said transistor gate, said continuous buried layer being vertically separated from said capacitor and said transistor.

Claim 3

A semiconductor memory device according to claim 1, wherein the peak value of the impurity concentration of said buried layer is in the range of 1×10 17 to 1×10 19 /cm 3 .

Claim 4

A semiconductor memory device according to claim 1, wherein the conductivity type of said substrate is of a P type, said capacitor is of a MOS type having a Hi-C structure with said Hi-C structure including an N layer and a P layer along the main surface of said substrate for providing an additional P-N junction capacitance, and said P layer and said buried layer are almost contiguously formed together in said substrate.

Claim 5

A semiconductor memory device according to claim 2, wherein the conductivity type of said substrate is of a P type, said capacitor is of a MOS type having a Hi-C structure, with said Hi-C structure including an N layer and a P layer along the main surface of said substrate for providing an additional P-N junction capacitance, and said P layer and said buried layer are almost contiguously formed together in said substrate.

Claim 6

A semiconductor memory device according to claim 1, wherein the conductivity type of said substrate is of an N type, said capacitor is of a MOS type having a Hi-C structure, with said Hi-C structure including a P layer and an N layer along the main surface of said substrate for providing an additional P-N junction capacitance, and said N layer and said buried layer are almost contiguously formed together in said substrate.

Claim 7

A semiconductor memory device according to claim 2, wherein the conductivity type of said substrate is of an N type, said capacitor is of a MOS type having a Hi-C structure, with said H-C structure including a P layer and an N layer along the main surface of said substrate for providing an additional P-N junction capacitance, and said N layer and said buried layer are almost contiguously formed together in said substrate.

Claim 8

A semiconductor memory device comprising: a semiconductor substrate of a certain conductivity type having a main surface, with said substrate having a prescribed impurity concentration for said certain conductivity type; a charge storage capacitor and a write/read transistor having a gate formed on said main surface; and a continuous buried layer formed at two depths in said substrate under both said write/read transistor and said charge storage capacitor and having an impurity concentration higher than that in said substrate for said certain conductivity type, wherein said continuous buried layer is formed at a first depth beneath the capacitor and at a second depth greater than the first depth beneath said transistor gate, said buried layer being vertically separated from said write/read transistor and said charge storage capacitor.

Claim 9

A semiconductor memory device comprising: a semiconductor substrate of a certain conductivity type having a main surface, with said substrate having a prescribed impurity concentration for said certain conductivity type; a charge storage capacitor and a write/read transistor having a gate formed on said main surface; and a continuous buried layer formed at two depths in said substrate under both said write/read transistor and said charge storage capacitor and having an impurity concentration higher than that in said substrate for said certain conductivity type, wherein said continuous buried layer is formed at a first depth beneath the capacitor and at a second depth greater than the first depth beneath said transistor gate, said buried layer being vertically separated from said write/read transistor and said charge storage capacitor.

Claim 10

A semiconductor memory device according to claim 7, wherein the peak value of the impurity concentration of said buried layer is in the range of 1×10 17 to 1×10 19 /cm 3 .

Claim 11

A semiconductor memory device according to claim 7, wherein the conductivity type of said substrate is of a P type, said capacitor is of a MOS type having a Hi-C structure with said Hi-C structure including an N layer and a P layer along the main surface of said substrate for providing an additional P-N junction capacitance, and said P layer and said buried layer are almost contiguously formed together in said substrate.

Claim 12

A semiconductor memory device according to claim 8, wherein the conductivity type of said substrate is of a P type, said capacitor is of a MOS type having a Hi-C structure, with said Hi-C structure including an N layer and a P layer along the main surface of said substrate for providing an additional P-N junction capacitance, and said P layer and said buried layer are almost contiguously formed together in said substrate.

Claim 13

A semiconductor memory device according to claim 7, wherein the conductivity type of said substrate is of an N type, said capacitor is of a MOS type having a Hi-C structure, with said Hi-C structure including a P layer and an N layer along the main surface of said substrate for providing an additional P-N junction capacitance, and said N layer and said buried layer are almost contiguously formed together in said substrate.

Claim 14

A semiconductor memory device according to claim 8, wherein the conductivity type of said substrate is of an N type, said capacitor is of a MOS type having a Hi-C structure, with said H-C structure including a P layer and an N layer along the main surface of said substrate for providing an additional P-N junction capacitance, and said N layer and said buried layer are almost contiguously formed together in said substrate.

Claim 15

A semiconductor memory device formed from: a semiconductor substrate of a first conductivity type with a first impurity concentration, and having a main surface, comprising: a charge storage capacitor and a write/read transistor having a gate; and a continuous buried layer having at least a first depth beneath the capacitor and a second depth greater than the first depth beneath said transistor gate, said continuous buried layer having an impurity concentration higher than said first impurity concentration, wherein said continuous buried layer is almost contiguously formed with said capacitor, and said continuous buried layer is vertically separated from said charge storage capacitor and said write/read transistor.

Claim 16

A semiconductor memory device formed from: a semiconductor substrate of a first conductivity type with a first impurity concentration, and having a main surface, comprising: a charge storage capacitor and a write/read transistor having a gate; and a continuous buried layer having at least a first depth beneath the capacitor and a second depth greater than the first depth beneath said transistor gate, said continuous buried layer having an impurity concentration higher than said first impurity concentration, wherein said continuous buried layer is almost contiguously formed with said capacitor, and said continuous buried layer is vertically separated from said charge storage capacitor and said write/read transistor.

Claim 17

A semiconductor memory device according to claim 11, wherein said capacitor is of a MOS type having a Hi-C structure with said Hi-C structure including an N layer and a P layer along the main surface of said substrate for providing an additional P-N junction capacitance.