Patent US5047712A successfully refreshed from Google Patents.
US5047712A
Expired / Lapsed
US
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Circuit for inverting the latter half of pattern output from device under test
Assignee: Ando Electric Co Ltd
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Filing: 1990-08-23
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Granted: 1991-09-10
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Expires: 2010-08-23
Abstract
Abstract A circuit for inverting the latter half of an expected signal representative of an output expected for a device to be tested with regard to operation thereof by a tester comprises a first flip-flop having a D-input terminal supplied with an inverting signal for controlling inversion of an expected pattern, a R-input terminal supplied with a reference clock signal for determining the period of the expected pattern and a C-input terminal supplied with a clock signal synchronized with transitions in an output pattern of a device to be tested as to whether it operates as desired or not, an exclusive-OR circuit having inputs supplied with the output of the first flip-flop and the expected pattern, respectively, an OR circuit having inputs supplied with the reference clock signal and the clock signal, respectively, and a second flip-flop having a D-input terminal supplied with the output of the exclusive-OR circuit and a C-input terminal supplied with the output of the OR circuit. Devices operating at higher operation cycles than that of the tester can be tested successfully.
Inventors
- 👤 Jou Koyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:20
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
157 words
A circuit for inverting the latter half of an expected pattern for a device to be tested with regard to operation thereof, comprising: a first flip-flop having a first input terminal supplied with an inverting signal for controlling inversion of an expected pattern, a second input terminal supplied with a reference clock signal for determining the period of said expected pattern and a third input terminal supplied with a clock signal synchronized with transitions in an output pattern of a device to be tested as to whether it operates as desired or not; an exclusive-OR circuit having inputs supplied with the output of said first flip-flop and said expected pattern, respectively; an OR circuit having inputs supplied with said reference clock signal and said clock signal, respectively; and a second flip-flop having a first input terminal supplied with the output of said exclusive-OR circuit and a third input terminal supplied with the output of said OR circuit.
Claim 2
Dependent Claim
157 words
A circuit for inverting the latter half of an expected pattern for a device to be tested with regard to operation thereof, comprising: a first flip-flop having a first input terminal supplied with an inverting signal for controlling inversion of an expected pattern, a second input terminal supplied with a reference clock signal for determining the period of said expected pattern and a third input terminal supplied with a clock signal synchronized with transitions in an output pattern of a device to be tested as to whether it operates as desired or not; an exclusive-OR circuit having inputs supplied with the output of said first flip-flop and said expected pattern, respectively; an OR circuit having inputs supplied with said reference clock signal and said clock signal, respectively; and a second flip-flop having a first input terminal supplied with the output of said exclusive-OR circuit and a third input terminal supplied with the output of said OR circuit.
Claim 3
Independent Claim
179 words
An apparatus for testing an electric/electronic device, comprising: a first flip-flop having a first input terminal supplied with an inverting signal for controlling inversion of an expected pattern, a second input terminal supplied with a reference clock signal for determining the period of said expected pattern and a third input terminal supplied with a clock signal synchronized with transitions in an output pattern of a device to be tested as to whether it operates as desired or not; a first exclusive-OR circuit having inputs supplied with the output of said first flip-flop and said expected pattern, respectively; an OR circuit having inputs supplied with said reference clock signal and said clock signal, respectively; a second exclusive-OR circuit having an inputs supplied with the output of said second flip-flop and an output pattern produced by said device under test, respectively; and a third flip-flop having inputs (first, third) supplied with the output of said second exclusive-OR circuit and a strobe signal, respectively, and an output terminal for producing a signal indicating whether said device under test operates satisfactorily or not.
Claim 4
Independent Claim
179 words
An apparatus for testing an electric/electronic device, comprising: a first flip-flop having a first input terminal supplied with an inverting signal for controlling inversion of an expected pattern, a second input terminal supplied with a reference clock signal for determining the period of said expected pattern and a third input terminal supplied with a clock signal synchronized with transitions in an output pattern of a device to be tested as to whether it operates as desired or not; a first exclusive-OR circuit having inputs supplied with the output of said first flip-flop and said expected pattern, respectively; an OR circuit having inputs supplied with said reference clock signal and said clock signal, respectively; a second exclusive-OR circuit having an inputs supplied with the output of said second flip-flop and an output pattern produced by said device under test, respectively; and a third flip-flop having inputs (first, third) supplied with the output of said second exclusive-OR circuit and a strobe signal, respectively, and an output terminal for producing a signal indicating whether said device under test operates satisfactorily or not.
References Cited (Backward Citations)
US4551837A
Cited
US4777616A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-09 | 1995-03-11 | 1995-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-09 | 1999-03-11 | 1999-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-09 | 2003-03-11 | 2003-09-10 | $7700.00 | Window Closed / Lapsed |