US5047659A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-overlapping two-phase clock generator utilizing floating inverters
Assignee: TDK Micronas GmbH
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Filing: 1990-09-04
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Granted: 1991-09-10
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Expires: 2010-09-04
Abstract
Abstract A two-phase clock generator generates a nonoverlapping two-phase clock from a unipolar input clock by utilizing gate delays in first and second signal paths. The output of each signal path is fed over a cross-coupled feedback path back to a logic gate in the respective other signal path. Each logic gate is a floating inverter having a first supply terminal connected to a supply voltage, and having a second supply terminal that is the feed point for the respective feedback signal from the output of the other signal path.
Inventors
- 👤 Manfred F. Ullrich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:00
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/151; H03K5/1515
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
174 words
A two-phase-clock generator which generates a first clock and a nonoverlapping second clock from an input clock by utilizing gate delays, comprising: a first floating inverter and a second floating inverter each having an input, an output, a first supply terminal and a second supply terminal, said input of said first logic gate and said input of said second logic gate being coupled to said input clock in antiphase, and said first supply terminals of each of said first and second floating inverters connected to a supply voltage; a first output buffer having an input coupled to said output of said first floating inverter and having an output that provides said first clock, said output further being provided as feedback to said second supply terminal of said second floating inverter; and a second output buffer having an input coupled to said output of said second floating inverter and having an output that provides said nonoverlapping second clock, said output further being provides as feedback to said second supply terminal of said first floating inverter.
Claim 2
Dependent Claim
174 words
A two-phase-clock generator which generates a first clock and a nonoverlapping second clock from an input clock by utilizing gate delays, comprising: a first floating inverter and a second floating inverter each having an input, an output, a first supply terminal and a second supply terminal, said input of said first logic gate and said input of said second logic gate being coupled to said input clock in antiphase, and said first supply terminals of each of said first and second floating inverters connected to a supply voltage; a first output buffer having an input coupled to said output of said first floating inverter and having an output that provides said first clock, said output further being provided as feedback to said second supply terminal of said second floating inverter; and a second output buffer having an input coupled to said output of said second floating inverter and having an output that provides said nonoverlapping second clock, said output further being provides as feedback to said second supply terminal of said first floating inverter.
Claim 3
Dependent Claim
52 words
The two-phase-clock generator as defined in claim 1, wherein: said first output buffer comprises a first buffer-inverter having its input connected directly to said output of said first floating inverter; and a second output buffer comprises a second buffer-inverter having its input connected directly to said output of said second floating inverter.
Claim 4
Dependent Claim
94 words
The two-phase-clock generator as defined in claim 2, wherein: said first and second floating inverters are CMOS inverters each comprising a P-channel transistor and an N-channel transistor, each transistor having a source terminal and a drain terminal; said source terminals of both P-channel transistors are connected to a positive supply voltage; said source terminal of the N-channel transistor in said first floating inverter is connected to said output of said second buffer-inverter; and said source terminal of said N-channel transistor in said second floating inverter is connected to said output of said first buffer-inverter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-09 | 1995-03-11 | 1995-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-09 | 1999-03-11 | 1999-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-09 | 2003-03-11 | 2003-09-10 | $7700.00 | Window Closed / Lapsed |