System for transferring test program information

Claim 1

A system for transmitting information from a source of designing electrical circuits to a source of manufacturing electrical circuits, which information is used in testing an electrical circuit at said source of manufacturing electrical circuits, comprising in combination: electric circuit design means formed to design at least one particular circuit; autogeneration means connected to said electrical circuit design means to receive information therefrom related to said particular circuit, said autogeneration means formed to create a compacted information program including truth table concepts, related to said particular circuit, whereby when said information program is implemented said truth table concepts cause certain aspects of said particular circuit to be tested; information communication means having first and second stations with said first station connected to said autogeneration means to receive said compacted information program therefrom, said first station formed to transmit said compacted information program to said second station; translation means connected to said second station to receive said compacted information program therefrom, said translation means formed to expand said compacted information program into said truth table concepts; and testing means connected to said translation means to receive said truth table concepts and formed to apply signals representing said truth table concepts to said particular circuit to effect testing thereof.

Claim 2

A system for transmitting information from a source of designing electrical circuits to a source of manufacturing electrical circuits, which information is used in testing an electrical circuit at said source of manufacturing electrical circuits, comprising in combination: electric circuit design means formed to design at least one particular circuit; autogeneration means connected to said electrical circuit design means to receive information therefrom related to said particular circuit, said autogeneration means formed to create a compacted information program including truth table concepts, related to said particular circuit, whereby when said information program is implemented said truth table concepts cause certain aspects of said particular circuit to be tested; information communication means having first and second stations with said first station connected to said autogeneration means to receive said compacted information program therefrom, said first station formed to transmit said compacted information program to said second station; translation means connected to said second station to receive said compacted information program therefrom, said translation means formed to expand said compacted information program into said truth table concepts; and testing means connected to said translation means to receive said truth table concepts and formed to apply signals representing said truth table concepts to said particular circuit to effect testing thereof.

Claim 10

A method for translating compacted information related to testing at least one circuit means, which one circuit means includes logic circuits and which one circuit means is formed to have a plurality of input means available for signals to be applied thereto and formed to have a plurality of output means available to have signals read therefrom, comprising the steps of: a) defining and generating, in machine readable language, a plurality of first phase signal concepts which are available to be employed to expand a compacted information program, and which first phase signal concepts include timing concepts, waveform concepts, and circuit hardware identifiers; b) defining and generating, in machine readable language, a plurality of group identifiers each of which represents a different collection of said first phase signal concepts; c) defining and generating, in machine readable language, a plurality of MACRO instructions each of which represents a different collection of group identifiers and alternatively a different collection of group identifiers plus other MACRO instructions; and d) defining and generating, in machine readable language, a plurality of different sets of vector signal concepts with each different set of vector signal concepts including selected ones of said MACRO instruction concepts.

Claim 11

A method for translating compacted information related to testing at least one circuit means, which one circuit means includes logic circuits and which one circuit means is formed to have a plurality of input means available for signals to be applied thereto and formed to have a plurality of output means available to have signals read therefrom, comprising the steps of: a) defining and generating, in machine readable language, a plurality of first phase signal concepts which are available to be employed to expand a compacted information program, and which first phase signal concepts include timing concepts, waveform concepts, and circuit hardware identifiers; b) defining and generating, in machine readable language, a plurality of group identifiers each of which represents a different collection of said first phase signal concepts; c) defining and generating, in machine readable language, a plurality of MACRO instructions each of which represents a different collection of group identifiers and alternatively a different collection of group identifiers plus other MACRO instructions; and d) defining and generating, in machine readable language, a plurality of different sets of vector signal concepts with each different set of vector signal concepts including selected ones of said MACRO instruction concepts.

Claim 12

A method for transferring information related to testing at least one circuit means, which one circuit means includes logic circuits and which one circuit means is formed to have a plurality of input means available for signals to be applied thereto and formed to have a plurality of output means available to have signals read therefrom, comprising the steps of: a) defining and generating, in machine readable language, a plurality of different waveforms to be used for application to selected ones of said input means and with each of said different waveforms having a different first identifier; b) defining and generating in machine readable language at least one cycle time in which certain test signals are applied; c) defining and generating, in machine readable language, different second identifiers each of which represents a different one of said input means to which certain signals may be applied; d) defining and generating, in machine readable language, different third identifiers each of which represents a different one of said output means from which signals may be read; e) defining and generating, in machine readable language, at least a fourth identifier for a particular one of said input means to have clock signals applied thereto; f) defining and generating, in machine readable language, different fifth identifiers each of which represents a different one of said logic circuits to which signals may be applied; g) defining and generating, in machine readable language, different first groups of associated signals with each of said first groups of associated signals having different sixth identifiers and with each of said first groups of associated signals including related ones of said first identifiers as well as others of said identifiers. h) defining and generating, in machine readable language, different second groups of associated signals with each of said second groups of associated signals having different seventh identifiers and with each of said second groups of associated signals including related ones of said second identifiers; i) defining and generating, in machine readable language, at least third groups of associated signal concepts which defines certain logic circuits and which has an eighth identifier; j) defining and generating, in machine readable language, a plurality of different MACRO instructions with each of said different MACRO instructions having a different ninth identifier and each MACRO instruction having selected different ones of said sixth, seventh and eighth identifiers; and k) defining and generating, in machine readable language, a plurality of different sets of vector signal concepts with each different set of vector signal concepts including selected ones of said ninth identifiers which in turn expand into sixth, seventh, and eighth identifiers which in turn expand into information signals, represented by said first, second, third, fourth and fifth identifiers to effect a test of said circuit means.

Claim 13

A method for transferring information related to testing at least one circuit means, which one circuit means includes logic circuits and which one circuit means is formed to have a plurality of input means available for signals to be applied thereto and formed to have a plurality of output means available to have signals read therefrom, comprising the steps of: a) defining and generating, in machine readable language, a plurality of different waveforms to be used for application to selected ones of said input means and with each of said different waveforms having a different first identifier; b) defining and generating in machine readable language at least one cycle time in which certain test signals are applied; c) defining and generating, in machine readable language, different second identifiers each of which represents a different one of said input means to which certain signals may be applied; d) defining and generating, in machine readable language, different third identifiers each of which represents a different one of said output means from which signals may be read; e) defining and generating, in machine readable language, at least a fourth identifier for a particular one of said input means to have clock signals applied thereto; f) defining and generating, in machine readable language, different fifth identifiers each of which represents a different one of said logic circuits to which signals may be applied; g) defining and generating, in machine readable language, different first groups of associated signals with each of said first groups of associated signals having different sixth identifiers and with each of said first groups of associated signals including related ones of said first identifiers as well as others of said identifiers. h) defining and generating, in machine readable language, different second groups of associated signals with each of said second groups of associated signals having different seventh identifiers and with each of said second groups of associated signals including related ones of said second identifiers; i) defining and generating, in machine readable language, at least third groups of associated signal concepts which defines certain logic circuits and which has an eighth identifier; j) defining and generating, in machine readable language, a plurality of different MACRO instructions with each of said different MACRO instructions having a different ninth identifier and each MACRO instruction having selected different ones of said sixth, seventh and eighth identifiers; and k) defining and generating, in machine readable language, a plurality of different sets of vector signal concepts with each different set of vector signal concepts including selected ones of said ninth identifiers which in turn expand into sixth, seventh, and eighth identifiers which in turn expand into information signals, represented by said first, second, third, fourth and fifth identifiers to effect a test of said circuit means.

Claim 14

A system for preparing compacted test information, at a site for designing high density electrical circuits, for use at a site for manufacturing electrical circuits, which test information is used in testing electrical circuits at said site for manufacturing electrical circuits, comprising in combination: CAD electric circuit design means formed to design at least one particular multicircuit; autogeneration means connected to said CAD electrical circuit design means to receive information therefrom related to said particular multicircuit, said autogeneration means formed to create a compacted test information program including truth table concepts in compacted vector format related to said particular circuit, whereby said test information program is directly decodable into said truth table concepts, in machine readable form, for use by a predetermined test platform to test certain aspects of said particular circuit to be tested, memory means adapted for receiving and storing said compacted test information, translation means adapted to be coupled to said memory means to receive said compacted test information program therefrom, said translation means formed to expand said compacted test information program into said truth table concepts, and to decode test procedures usable by said predetermined test platform, and test platform means connected to said translation means to receive said truth table concepts and said test procedures and formed to apply signals representing said truth table concepts and said test procedures to said particular multicircuit to effect testing thereof.

Claim 15

A system for preparing compacted test information, at a site for designing high density electrical circuits, for use at a site for manufacturing electrical circuits, which test information is used in testing electrical circuits at said site for manufacturing electrical circuits, comprising in combination: CAD electric circuit design means formed to design at least one particular multicircuit; autogeneration means connected to said CAD electrical circuit design means to receive information therefrom related to said particular multicircuit, said autogeneration means formed to create a compacted test information program including truth table concepts in compacted vector format related to said particular circuit, whereby said test information program is directly decodable into said truth table concepts, in machine readable form, for use by a predetermined test platform to test certain aspects of said particular circuit to be tested, memory means adapted for receiving and storing said compacted test information, translation means adapted to be coupled to said memory means to receive said compacted test information program therefrom, said translation means formed to expand said compacted test information program into said truth table concepts, and to decode test procedures usable by said predetermined test platform, and test platform means connected to said translation means to receive said truth table concepts and said test procedures and formed to apply signals representing said truth table concepts and said test procedures to said particular multicircuit to effect testing thereof.