Patent US5045997A successfully refreshed from Google Patents.
US5045997A
Expired / Lapsed
US
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Data processor
Assignee: Mitsubishi Electric Corp
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Filing: 1988-10-28
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Granted: 1991-09-03
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Expires: 2008-10-28
Abstract
Abstract The efficiency of a processor in which a packet is stored in a receiver buffer, processed in a central processing unit, and sent out via a transmitter buffer, is low. According to the invention, data is transferred to a high-speed memory via the receiver memory. When the high-speed memory is filled with data, the data is processed by the CPU, and the packet is transmitted from the high-speed memory via the transmitter memory. A competition control section is provided to control data accesses in the sequential operation.
Inventors
- 👤 Akira Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:43
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
308 words
A data processor to be connected to another data processor via a bus for transmitting or receiving data to execute a predetermined process, which comprises: (a) a central processing unit; (b) a high-speed memory; and (c) a memory competition circuit, said memory competition circuit including: (i) an input data memory connected to said bus for temporarily storing data to be input to said high-speed memory from said bus; (ii) an output data memory connected to said high-speed memory for temporarily storing data to be output to said bus from said high-speed memory; (iii) a read register connected to said high-speed memory for temporarily latching data read out of said high-speed memory by said central processing unit; (iv) a write register connected to said central processing unit for temporarily latching data to be written in said high-speed memory by said central processing unit; (v) a competition control section connected to said input and output data memories and said central processing unit for receiving a write request from said input data memory, a read request from said output data memory, a read request from said central processing unit, and a write request from said central processing unit to execute access to said high-speed memory by said requests according to a predetermined priority order among said input data memory, output data memory, read register and write register, or issuing a wait signal to said central processing unit when access is not in time, (vi) a clock generator for generating a clock signal independent of that of said central processing unit; (vii) a synchronizing circuit connected to said clock generator for synchronizing access requests to be input to said memory competition circuit; and (viii) an arbiter connected to said synchronizing circuit for selecting a request of the highest priority to control competition among said access requests for access to said high-speed memory.
Claim 2
Dependent Claim
308 words
A data processor to be connected to another data processor via a bus for transmitting or receiving data to execute a predetermined process, which comprises: (a) a central processing unit; (b) a high-speed memory; and (c) a memory competition circuit, said memory competition circuit including: (i) an input data memory connected to said bus for temporarily storing data to be input to said high-speed memory from said bus; (ii) an output data memory connected to said high-speed memory for temporarily storing data to be output to said bus from said high-speed memory; (iii) a read register connected to said high-speed memory for temporarily latching data read out of said high-speed memory by said central processing unit; (iv) a write register connected to said central processing unit for temporarily latching data to be written in said high-speed memory by said central processing unit; (v) a competition control section connected to said input and output data memories and said central processing unit for receiving a write request from said input data memory, a read request from said output data memory, a read request from said central processing unit, and a write request from said central processing unit to execute access to said high-speed memory by said requests according to a predetermined priority order among said input data memory, output data memory, read register and write register, or issuing a wait signal to said central processing unit when access is not in time, (vi) a clock generator for generating a clock signal independent of that of said central processing unit; (vii) a synchronizing circuit connected to said clock generator for synchronizing access requests to be input to said memory competition circuit; and (viii) an arbiter connected to said synchronizing circuit for selecting a request of the highest priority to control competition among said access requests for access to said high-speed memory.
Claim 3
Dependent Claim
67 words
The data processor of claim 1, wherein said memory competition circuit comprises: a receiver counter; a transmitter counter; and means responsive to a count signal from said receiver or transmitter counter to manage addresses within said high-speed memory and switches an area of said high-speed memory between receiver and transmitter buffers for controlling transmission and reception between said input or output data memory and said high-speed memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-02 | 1995-03-04 | 1995-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-02 | 1999-03-04 | 1999-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-02 | 2003-03-04 | 2003-09-03 | $7700.00 | Window Closed / Lapsed |