Digitally controlled variable resistor

Claim 2

A variable resistor, comprising: a pair of terminals for providing a variable resistance to an external circuit; a plurality of individual resistances connected in series between the pair of terminals, each individual resistance including a compensating resistance and a basic resistance; a plurality of electronic switches, each electronic switch being connected in a parallel with an associated one of the individual resistances, wherein each of the electronic switches, when in a closed state, exhibits a significant resistance, corresponding to the compensating resistance, and effectively shorts out the associated individual resistance; and latch means capable of receiving and holding a data signal and having outputs controlling the switching of the electronic switches between open and closed states, so that the value of resistance between the pair of terminals can be set by the data signal.

Claim 3

A variable resistor, according to claim 1, wherein the latch means holds a binary number and the outputs provide respective bits of the binary number, the value of each bit determining whether a respective one of the electronic switches is in an open or closed state.

Claim 4

A variable resistor, according to claim 1, wherein the basic values of the individual resistances proportionally follow the progression 2 0 , 2 1 , 2 2 , 2 3 , and so on.

Claim 5

A variable resistor, according to claim 1, wherein the compensating resistance is r/x, where the respective individual resistance values follow the progression 2 0 +r, 2 1 +r, 2 2 +r, 2 3 +r, and so on, where r is the minimum resistance between the terminals occurring when all of the switches are the closed state, and where x is the number of the individual resistances

Claim 6

A variable resistor, according to claim 1, wherein the electronic switches include field-effect transistors.

Claim 7

A variable resistor, according to claim 1, wherein the individual resistances, the electronic switches and the latch means are formed in a solid state integrated circuit chip.

Claim 8

A variable resistor, according to claim 1, further comprising a shift register having a serial data input for receiving the data signal, and a set of parallel outputs connected to the latch means.

Claim 9

An electronic circuit, comprising: a plurality of resistance networks, each network for providing a variable resistance between an associated pair of terminals; a plurality of switches, coupled to the resistor network, for changing the variable resistances; a plurality of latches for controlling the plurality of switches, each latch including a data input, a data output and an enable input for enabling data to be transferred from the data input and held on the data output; a shift register having a serial data input, a first parallel data output connected to a data bus, and a second parallel data output, the data bus connected in parallel to the data input of the latches; and a decoder having an input coupled to the second parallel data output and outputs coupled to respective enable inputs of the latches, so that a selected latch is enabled to receive data from the data bus as selected by data from the second outputs of the shift register; wherein the electronic switches are controlled by the data output of the latch so that the resistance between each pair of terminals is set in accordance with the data held on the outputs of the latch.

Claim 10

An electronic circuit, comprising: a plurality of resistance networks, each network for providing a variable resistance between an associated pair of terminals; a plurality of switches, coupled to the resistor network, for changing the variable resistances; a plurality of latches for controlling the plurality of switches, each latch including a data input, a data output and an enable input for enabling data to be transferred from the data input and held on the data output; a shift register having a serial data input, a first parallel data output connected to a data bus, and a second parallel data output, the data bus connected in parallel to the data input of the latches; and a decoder having an input coupled to the second parallel data output and outputs coupled to respective enable inputs of the latches, so that a selected latch is enabled to receive data from the data bus as selected by data from the second outputs of the shift register; wherein the electronic switches are controlled by the data output of the latch so that the resistance between each pair of terminals is set in accordance with the data held on the outputs of the latch.

Claim 11

An electronic circuit, according to claim 8, wherein each network includes a series of individual resistances, and each of the individual resistance is arranged in parallel with one of the electronic switches, whereby when a switch is closed that individual resistance is shorted out from the series of individual resistances.

Claim 12

An electronic circuit, according to claim 9, wherein each electronic switch includes a significant resistance when it is in a closed state, and each individual resistance includes a basic resistance and a compensating resistance that corresponds to the significant resistance of the electronic switch, such that compensating resistance will be included for each individual resistance and associated electronic switch, irrespective of whether the electronic switch is in a closed state.

Claim 13

An electronic circuit, according to claim 8, wherein each latch holds a binary number and the data output of the latch includes a plurality of single-bit outputs providing respective bits of the binary number, the value of each bit determining whether a respective one of the electronic switches is in an open or closed state.

Claim 14

An electronic circuit, according to claim 9, wherein the values of the individual resistances in at least one of the networks proportionally follow the progression 2 0 , 2 1 , 2 2 , 2 3 , and so on.

Claim 15

An electronic circuit, according to claim 8, wherein the electronic switches and the latches are formed in a solid state integrated circuit chip.

Claim 16

An integrated circuit formed in a semiconductor chip, the integrated circuit comprising: a plurality of latches, each of the latches including a data input, a data output, and an enable input for enabling data to be transferred from the data input and held on the data output; a shift register having a serial data input, a first parallel data output connected to a data bus, and a second parallel data output coupled to the enable inputs of the latches, the data bus connecting in parallel with the data inputs of the latches; and for each latch, a respective pair of terminals for providing a variable resistance to an external circuit, a plurality of individual resistances and a plurality of associated electronic switches connected in series between the pair of terminals, wherein each individual resistance includes a basic resistance and a compensating resistance and is connected in parallel to one of the associated electronic switches whereby when a switch is closed that individual resistance is shorted out from the series of individual resistances, wherein the data output of the latch includes single-bit outputs controlling the switching of the electronic switches between open and closed states, so that the value of resistance between the pair of terminals can be set by the data signal held on the data output of the latch.

Claim 17

An integrated circuit formed in a semiconductor chip, the integrated circuit comprising: a plurality of latches, each of the latches including a data input, a data output, and an enable input for enabling data to be transferred from the data input and held on the data output; a shift register having a serial data input, a first parallel data output connected to a data bus, and a second parallel data output coupled to the enable inputs of the latches, the data bus connecting in parallel with the data inputs of the latches; and for each latch, a respective pair of terminals for providing a variable resistance to an external circuit, a plurality of individual resistances and a plurality of associated electronic switches connected in series between the pair of terminals, wherein each individual resistance includes a basic resistance and a compensating resistance and is connected in parallel to one of the associated electronic switches whereby when a switch is closed that individual resistance is shorted out from the series of individual resistances, wherein the data output of the latch includes single-bit outputs controlling the switching of the electronic switches between open and closed states, so that the value of resistance between the pair of terminals can be set by the data signal held on the data output of the latch.

Claim 18

An integrated circuit, according to claim 14, wherein each latch holds a binary number and the single-bit outputs provide respective bits of the binary number, the value of each bit determining whether a respective one of the electronic switches is in an open or closed state.

Claim 19

An integrated circuit, according to claim 14, wherein the values of the basic resistances proportionally follow the progression 2 0 , 2 1 , 2 2 , 2 3 , and so on.

Claim 20

An integrated circuit, according to claim 14, wherein the compensating resistance will be included for each individual resistance and associated electronic switch, irrespective of whether the electronic switch is in a closed state.

Claim 21

An integrated circuit, according to claim 14, wherein the electronic switches, when in their closed state, have a significant resistance which corresponds to the compensating resistance which has a value of r/x, where the respective basic values follow the progression 2 0 , 2 1 , 2 2 , 2 3 , and so on, where r is the minimum resistance between the terminals occurring when all of the switches are closed, and where x is the number of the individual resistances.

Claim 22

An integrated circuit, according to claim 14, wherein the electronic switches include field-effect transistors.

Claim 23

An integrated circuit, according to claim 14, further comprising a decoder having an input connected to the second parallel data output, and outputs coupled to respective enable inputs of the latches, so that only a selected latch is enabled to receive data from the data bus as selected by data from the second output of the shift register.