Amplifying circuit

Claim 2

An amplifying circuit comprising a plurality of signal input circuits for multi-channel input, each of which receives a corresponding signal input, a load circuit commonly connected to the outputs of the signal input circuits, an output terminal connected to said load circuit, a current source responsive to a voltage being applied thereto for supplying a current, selecting means for selectively connecting said current source to one of said signal input circuits and for applying a voltage to said current source in response to selection data, said voltage lowering during a transient period in which said selection data changes, and dummy channel means connected to said load circuit and said current source and responsive to said lowering of voltage during said transient period to connect said current source to said load circuit without passing through said signal input circuits.

Claim 3

An amplifying circuit according to claim 1, wherein said dummy channel means includes a differential type transistor circuit connected to said load circuit and an additional transistor responsive to lowering of said voltage for connecting said current source with said differential type transistor circuit to supply current to said load circuit.

Claim 4

An amplifying circuit according to claim 1, wherein said selecting means includes respective switch transistors for each signal input circuit, each switch transistor being connected to said current source for applying a voltage thereto when said switch transistor is rendered conductive, and means for selectively applying a voltage to each switch transistor to render said switch transistor conductive and thereby apply a voltage to said current source.

Claim 5

An amplifying circuit according to claim 3, wherein said dummy channel means includes a differential type transistor circuit connected to said load circuit and an additional transistor responsive to lowering of said voltage for connecting said current source with said differential type circuit to supply current to said load circuit.

Claim 6

An amplifying circuit according to claim 4, wherein the voltage applied to each switch transistor is a bias voltage and wherein means are provided for applying a bias voltage to said additional transistor, which is lower than the bias voltage applied to any of said switch transistors.

Claim 7

An amplifying circuit comprising a plurality of signal input circuits each of which has a first transistor and a second transistor connected with each other to form a differential type circuit, input means for respectively applying a corresponding input signal to the bases of the first and the second transistors, load circuits, connection means which commonly connect said signal input circuits with said load circuits, a current source, a plurality of third transistors through each of which said current source is connected to a common emitter point of said first and second transistors, selecting means responsive to selection data for making one of the third transistors conductive, fourth transistors whose collectors are connected respectively to said load circuits and whose bases are connected to a source of bias current, a fifth transistor through which the emitters of said fourth transistors are connected to said current source and means which renders said fifth transistor conductive in a transient period in which the content of said selection data changes.

Claim 8

An amplifying circuit comprising a plurality of signal input circuits each of which has a first transistor and a second transistor connected with each other to form a differential type circuit, input means for respectively applying a corresponding input signal to the bases of the first and the second transistors, load circuits, connection means which commonly connect said signal input circuits with said load circuits, a current source, a plurality of third transistors through each of which said current source is connected to a common emitter point of said first and second transistors, selecting means responsive to selection data for making one of the third transistors conductive, fourth transistors whose collectors are connected respectively to said load circuits and whose bases are connected to a source of bias current, a fifth transistor through which the emitters of said fourth transistors are connected to said current source and means which renders said fifth transistor conductive in a transient period in which the content of said selection data changes.

Claim 9

An amplifying circuit according to claim 6, wherein said means for making one of said third transistors conductive includes means for providing a bias voltage to said third transistor and said means which renders said fifth transistor conductive includes means for applying a bias voltage to said fifth transistor lower than the bias voltage applied to said third transistor.