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US3594590A Expired / Lapsed US ⏱️ 0.0 years remaining

Memory sense amplifier

Assignee: United States Department of the Navy
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Filing: 1968-12-09
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Granted: 1971-07-20
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Expires: 1988-12-09
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Abstract

Abstract A multiple channel gated computer memory sense amplifier is provided having a multiplicity of inputs which are amplified by a multiplicity of preamplifiers in a predetermined timed sequence prior to linear amplification and buffering. The amplifier is gated in its preamplifier unit such time as the preamplifier is to be rendered operative. Switching transients are eliminated by providing a bridge circuit to carry the biasing current when the preamplifiers are in standby condition.

Inventors

  • 👤 Kirk W Smith

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 01:01
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 146 words
A memory sense amplifier comprising: a resistance bridge circuit having a pair of output corners and a pair of input corners; a source of potential voltage, one side of said source being connected to a reference potential and the other side of said source being connected to one of said input corners; a preamplifier, said preamplifier including a pair of transistors, each of said transistors having one terminal adapted to receive an input signal and a pair of energizing terminals across which a potential voltage must be applied to render each of said transistors operative, one energizing terminal of each transistor being connected to a different output corner of said bridge circuit, the other energizing terminal of each transistor being interconnected to form a common terminal; and means for connecting said common terminal or the other input corner of said bridge circuit to said reference potential.
Claim 2
Dependent Claim 146 words
A memory sense amplifier comprising: a resistance bridge circuit having a pair of output corners and a pair of input corners; a source of potential voltage, one side of said source being connected to a reference potential and the other side of said source being connected to one of said input corners; a preamplifier, said preamplifier including a pair of transistors, each of said transistors having one terminal adapted to receive an input signal and a pair of energizing terminals across which a potential voltage must be applied to render each of said transistors operative, one energizing terminal of each transistor being connected to a different output corner of said bridge circuit, the other energizing terminal of each transistor being interconnected to form a common terminal; and means for connecting said common terminal or the other input corner of said bridge circuit to said reference potential.
Claim 3
Dependent Claim 294 words
Apparatus for selectively coupling the outputs of a number of the memory elements of a computer to an output circuit, comprising: a plurality of normally inactivated preamplifiers corresponding in number to said number of memory elements, each of said preamplifiers including a pair of transistors and each of said transistors having a pair of terminals across which a potential voltage must be applied to render them operative; means for coupling the input of each preamplifier to a different memory element output such that any signal appearing in the output of any memory element is subjected to preamplification when the preamplifier coupled thereto is activated; means for coupling the output of each preamplifiers to said output circuit; and means for selectively activating only one of said preamplifiers at any one time, said last-mentioned means including a source of potential voltage, one side of said source being connected to a reference potential; a resistance bridge having an input pair of corners and an output pair of corners; means for connecting one of said input corners to the other side of said source means for connecting one terminal of each transistor of each pair to different output corners of said bridge; means for interconnecting the other terminals of each pair of transistors so as to form a plurality of common terminals corresponding in number to the number of said preamplifiers; and means for connecting the different common terminals one at a time to said reference potential and for connecting the other of said input corners to said reference potential whenever none of said common terminals is connected to said reference potential, whereby the potential voltage at said one terminal of each transistor remains constant, thus eliminating any transient which may occur when said preamplifiers are selectively activated.
Claim 4
Dependent Claim 294 words
Apparatus for selectively coupling the outputs of a number of the memory elements of a computer to an output circuit, comprising: a plurality of normally inactivated preamplifiers corresponding in number to said number of memory elements, each of said preamplifiers including a pair of transistors and each of said transistors having a pair of terminals across which a potential voltage must be applied to render them operative; means for coupling the input of each preamplifier to a different memory element output such that any signal appearing in the output of any memory element is subjected to preamplification when the preamplifier coupled thereto is activated; means for coupling the output of each preamplifiers to said output circuit; and means for selectively activating only one of said preamplifiers at any one time, said last-mentioned means including a source of potential voltage, one side of said source being connected to a reference potential; a resistance bridge having an input pair of corners and an output pair of corners; means for connecting one of said input corners to the other side of said source means for connecting one terminal of each transistor of each pair to different output corners of said bridge; means for interconnecting the other terminals of each pair of transistors so as to form a plurality of common terminals corresponding in number to the number of said preamplifiers; and means for connecting the different common terminals one at a time to said reference potential and for connecting the other of said input corners to said reference potential whenever none of said common terminals is connected to said reference potential, whereby the potential voltage at said one terminal of each transistor remains constant, thus eliminating any transient which may occur when said preamplifiers are selectively activated.
Claim 5
Dependent Claim 247 words
Apparatus for selectively amplifying the outputs of an number of computer memory elements comprising, in combination: a plurality of normally inactivated preamplifiers corresponding in number to said number of elements, each of said preamplifiers having an input coupled to a different memory element output and including a pair of transistors, each of said transistors having a pair of terminals across which a potential voltage must be applied to render each of said transistors operative; means for amplifying the outputs of all of said preamplifiers; and means for selectively activating only one of said preamplifiers at one time, said activating means including a source of potential voltage, onE side of said source being connected to a reference potential; a resistance bridge having an input pair of corners and an output pair of corners; means for connecting one of said input corners to the other side of said source; means for connecting one terminal of each transistor of each pair to different output corners of said bridge; means for interconnecting the other terminals of said pair of transistors so as to form a reference potential terminal; and means for switching said reference potential to the reference potential terminal of that preamplifier which is to be activated or to the other input corner of said bridge when ever none of said preamplifiers are activated, whereby the potential voltage at said one terminal of each transistor remains constant, thus eliminating any transient which may occur when said preamplifiers are selectively activated.
Claim 6
Dependent Claim 247 words
Apparatus for selectively amplifying the outputs of an number of computer memory elements comprising, in combination: a plurality of normally inactivated preamplifiers corresponding in number to said number of elements, each of said preamplifiers having an input coupled to a different memory element output and including a pair of transistors, each of said transistors having a pair of terminals across which a potential voltage must be applied to render each of said transistors operative; means for amplifying the outputs of all of said preamplifiers; and means for selectively activating only one of said preamplifiers at one time, said activating means including a source of potential voltage, onE side of said source being connected to a reference potential; a resistance bridge having an input pair of corners and an output pair of corners; means for connecting one of said input corners to the other side of said source; means for connecting one terminal of each transistor of each pair to different output corners of said bridge; means for interconnecting the other terminals of said pair of transistors so as to form a reference potential terminal; and means for switching said reference potential to the reference potential terminal of that preamplifier which is to be activated or to the other input corner of said bridge when ever none of said preamplifiers are activated, whereby the potential voltage at said one terminal of each transistor remains constant, thus eliminating any transient which may occur when said preamplifiers are selectively activated.
Claim 7
Dependent Claim 51 words
The apparatus as recited in claim 3 further including; a buffer amplifier; AC coupling means connected between the output of said amplifying means and the input of said buffer amplifier; and means for connecting the input of said buffer amplifier to said reference potential whenever none of said preamplifiers is activated.

References Cited (Backward Citations)

US2572792A Cited
US2867723A Cited
US3241078A Cited
US3452289A Cited
US3478283A Cited
US3454893A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-07-19 1975-01-18 1975-07-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-07-19 1979-01-18 1979-07-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-07-19 1983-01-18 1983-07-20 $7700.00 Window Closed / Lapsed

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