Patent US5045639A successfully refreshed from Google Patents.
US5045639A
Expired / Lapsed
US
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Pin grid array package
Assignee: Tong Hsing Electronic Industries Ltd
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Filing: 1990-08-21
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Granted: 1991-09-03
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Expires: 2010-08-21
Abstract
Abstract A pin grid array package having a substrate formed from a ceramics containing a 90% or higher alumina composition. The substrate has an palladium-silver layer on an upper surface thereof with a silver layer further provided on the Pd-Ag layer and a gold bonding pad on a outer periphery of a cavity of the substrate so as to provide electrical connection between pins and chip. The Ag layer is covered with a dielectric layer to prevent contamination from moisture.
Inventors
- 👤 Henry Liu
- 👤 Heinz Ru
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:47
CPC Classifications
H; H10; H10W; H10W42/00; H10W70/00; H10W70/60; H10W70/62; H10W70/63; H10W70/635; H10W70/66
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
168 words
A pin grid array package comprising: a substrate being made out of a dry molded ceramic with at least a 90% concentration of Al 2 O 3 , and formed by using a thick-film method, said substrate having a cavity adapted for receiving a chip, a plurality of through-holes drilled for receiving pins made from a copper material and plated with Ni and Au, a Pd/Ag layer with a donut shape surrounding all said through-holes on an upper surface of said substrate; an Ag layer being provided as traces to form connection between said upper Pd/Ag layer and Au bonding pads provided on an outer periphery of said cavity of said substrate, which provide electrical connection between the pins and chip, a dielectric layer being provided on said Ag layer to prevent migration and contamination from moisture; and a window frame with a sealing glass formed on a lower surface thereof being provided to encompass said dielectric layer and the chip received in said cavity of said substrate.
Claim 2
Dependent Claim
168 words
A pin grid array package comprising: a substrate being made out of a dry molded ceramic with at least a 90% concentration of Al 2 O 3 , and formed by using a thick-film method, said substrate having a cavity adapted for receiving a chip, a plurality of through-holes drilled for receiving pins made from a copper material and plated with Ni and Au, a Pd/Ag layer with a donut shape surrounding all said through-holes on an upper surface of said substrate; an Ag layer being provided as traces to form connection between said upper Pd/Ag layer and Au bonding pads provided on an outer periphery of said cavity of said substrate, which provide electrical connection between the pins and chip, a dielectric layer being provided on said Ag layer to prevent migration and contamination from moisture; and a window frame with a sealing glass formed on a lower surface thereof being provided to encompass said dielectric layer and the chip received in said cavity of said substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-02 | 1995-03-04 | 1995-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-02 | 1999-03-04 | 1999-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-02 | 2003-03-04 | 2003-09-03 | $7700.00 | Window Closed / Lapsed |