DRAM cell having a texturized polysilicon lower capacitor plate for increased capacitance

Abstract

Abstract A DRAM cell having enhanced capacitance attributable to the use of a textured polycrystalline silicon storage-node capacitor plate. The present invention is particularly applicable to DRAM cells which employ a stacked-capacitor design, as such designs generally a conductively-doped polycrystalline silicon layer as the storage-node, or lower, capacitor plate. A poly texturization process imparts a three-dimensional texturized character to the upper surface of the storage-node plate. Texturization is accomplished by subjecting the storage-node plate layer to a wet oxidation step. Since oxidation at the crystal grain boundaries on the surface of the poly layer proceeds more rapidly than elsewhere, the surface becomes bumpy. When maximum texturization has been achieved, the overlying oxide is removed during a wet etch step. With texturization complete, a thin (70-100 angstroms thick) silicon nitride layer is deposited on top of the texturized poly layer, followed by the deposition of a second poly layer, which functions as the capacitor field plate. Since the nitride layer is thin in comparison to the bumps on the surface of the storage-node plate layer, capacitive area is substantially augmented. Cell capacitance can be increased approximately thirty percent using a storage-node plate so texturized.

Inventors

• 👤 Pierre C. Fazan
• 👤 Ruojia R. Lee

Bibliographic Details