US5043731A
Expired / Lapsed
US
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Digital-to-analog converter having a ladder type resistor network
Assignee: Fujitsu VLSI Ltd
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Filing: 1990-08-14
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Granted: 1991-08-27
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Expires: 2010-08-14
Abstract
Abstract A digital-to-analog converter includes a ladder type resistor network having stages equal in number to bits of a digital input signal, each of the stages including a first resistor and a second resistor mutually connected in series via a node. A first switch, which is provided for each of the stages, selectively supplies either an upper limit voltage or a lower limit voltage to a corresponding one of the stages in accordance with a logical value of a corresponding one of the bits of the digital input signal. An analog signal output terminal is coupled to the node of one of the stages which corresponds to a most significant bit of the digital input signal. An analog output signal is output via the analog signal output terminal. An offset level control resistor has a first end connected to the node of one of the stages which corresponds to a least significant bit of the digital input signal and a second end. A second switch, which is coupled to the second end of the offset level control resistor, selectively supplies either the upper limit voltage or the lower limit voltage to the second end of the offset level control resistor.
Inventors
- 👤 Hirokazu Nishimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:45
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/06; H03M1/0602; H03M1/0604; H03M1/0607; H03M1/66; H03M1/74; H03M1/78; H03M1/785
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
218 words
A digital-to-analog converter comprising: a ladder type resistor network having stages equal in number to bits of a digital input signal, each of said stages including a first resistor and a second resistor mutually connected in series via a node; first switching means, provided for each of said stages, for selectively supplying either an upper limit voltage or a lower limit voltage to a corresponding one of said stages in accordance with a logical value of a corresponding one of said bits of the digital input signal; an analog signal output terminal coupled to the node of one of the stages which corresponds to a most significant bit of said digital input signal, an analog output signal being output via said analog signal output terminal; an offset level control resistor having a first end connected to the node of one of the stages which corresponds to a predetermined significant bit of said digital input signal selected from a group consisting of said most significant bit and a least significant bit of said digital input signal and having a second end; and second switching means, coupled to the second end of said offset level control resistor, for selectively supplying either said upper limit voltage or said lower limit voltage to the second end of said offset level control resistor.
Claim 2
Dependent Claim
218 words
A digital-to-analog converter comprising: a ladder type resistor network having stages equal in number to bits of a digital input signal, each of said stages including a first resistor and a second resistor mutually connected in series via a node; first switching means, provided for each of said stages, for selectively supplying either an upper limit voltage or a lower limit voltage to a corresponding one of said stages in accordance with a logical value of a corresponding one of said bits of the digital input signal; an analog signal output terminal coupled to the node of one of the stages which corresponds to a most significant bit of said digital input signal, an analog output signal being output via said analog signal output terminal; an offset level control resistor having a first end connected to the node of one of the stages which corresponds to a predetermined significant bit of said digital input signal selected from a group consisting of said most significant bit and a least significant bit of said digital input signal and having a second end; and second switching means, coupled to the second end of said offset level control resistor, for selectively supplying either said upper limit voltage or said lower limit voltage to the second end of said offset level control resistor.
Claim 3
Dependent Claim
41 words
A digital-to-analog converter as claimed in claim 1, wherein said second switching means selectively supplies either said upper limit voltage or said lower limit voltage in accordance with the logical value of said most significant bit of said digital input signal.
Claim 4
Dependent Claim
41 words
A digital-to-analog converter as claimed in claim 2, wherein when the most significant bit of said digital input signal is binary zero, said second switching means supplies said lower limit voltage to the second end of said offset level control resistor.
Claim 5
Dependent Claim
41 words
A digital-to-analog converter as claimed in claim 2, wherein when the most significant bit of said digital input signal is binary one, said second switching means supplies said upper limit voltage to the second end of said offset level control resistor.
Claim 6
Dependent Claim
67 words
A digital-to-analog converter as claimed in claim 2, wherein when the logical value of said most significant bit of said digital input signal changes from binary zero to binary one, said second switching means stops supplying said lower limit voltage to the second end of said offset level control resistor and starts supplying the upper limit voltage to the second end of said offset level control resistor.
Claim 7
Dependent Claim
38 words
A digital-to-analog converter as claimed in claim 2, wherein said second switching means comprises decoder means for decoding the most significant bit of said digital input signal and for outputting said logical value of the most significant bit.
Claim 8
Dependent Claim
64 words
A digital-to-analog converter as claimed in claim 6, wherein: said decoder means comprises a CMOS inverter connected between said upper limit voltage and said lower limit voltage; and said CMOS inverter has an input terminal for receiving the most significant bit of said digital input signal through an inverter and an output terminal connected to the second end of said offset level control resistor.
Claim 9
Dependent Claim
21 words
A digital-to-analog converter as claimed in claim 1, wherein said second resistor has a resistance twice that of said first resistor.
Claim 10
Dependent Claim
68 words
A digital-to-analog converter as claimed in claim 1, wherein: said ladder type resistor network comprises eight stages; said digital input signal is composed of eight bits; and when said most significant bit of said digital input signal changes from "01111111" to "10000000", said second switching means supplies said upper limit voltage to the second end of said offset level control resistor in place of said lower limit voltage.
Claim 11
Dependent Claim
30 words
A digital-to-analog converter as claimed in claim 1, further comprising third switching means for supplying said second switching means with either said upper limit voltage or said lower limit voltage.
Claim 12
Dependent Claim
199 words
A digital-to-analog converter comprising: a ladder type resistor network having stages equal in number to bits of a digital input signal, each of said stages including a first resistor and a second resistor mutually connected in series via a node; switching means, provided for each of said stages, for selectively supplying either an upper limit voltage or a lower limit voltage to a corresponding one of said stages in accordance with a logical value of a corresponding one of said bits of the digital input signal; an analog signal output terminal coupled to the node of one of the stages which corresponds to a most significant bit of said digital input signal, an analog output signal being output via said analog signal output terminal; and an offset level control resistor having a first end connected to the node of one of the stages which corresponds to a least significant bit of said digital input signal and a second end connected directly to an output terminal of said switching means corresponding to the most significant bit of said digital input signal, a selected one of said upper limit voltage and said lower limit voltage being drawn from said output terminal.
Claim 13
Dependent Claim
199 words
A digital-to-analog converter comprising: a ladder type resistor network having stages equal in number to bits of a digital input signal, each of said stages including a first resistor and a second resistor mutually connected in series via a node; switching means, provided for each of said stages, for selectively supplying either an upper limit voltage or a lower limit voltage to a corresponding one of said stages in accordance with a logical value of a corresponding one of said bits of the digital input signal; an analog signal output terminal coupled to the node of one of the stages which corresponds to a most significant bit of said digital input signal, an analog output signal being output via said analog signal output terminal; and an offset level control resistor having a first end connected to the node of one of the stages which corresponds to a least significant bit of said digital input signal and a second end connected directly to an output terminal of said switching means corresponding to the most significant bit of said digital input signal, a selected one of said upper limit voltage and said lower limit voltage being drawn from said output terminal.
Claim 14
Dependent Claim
69 words
A digital-to-analog converter as claimed in claim 11, wherein: said switching means corresponding to the most significant bit of said digital input signal comprises a CMOS inverter connected between said upper limit voltage and said lower limit voltage; and said CMOS inverter has an input terminal for receiving the most significant bit of said digital input signal and said output terminal connected directly to said offset level control resistor.
Claim 15
Dependent Claim
25 words
A digital-to-analog converter as claimed in claim 11, wherein said CMOS inverter receives the most significant bit of said digital input signal through an inverter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-26 | 1995-02-25 | 1995-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-26 | 1999-02-25 | 1999-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-26 | 2003-02-25 | 2003-08-27 | $7700.00 | Window Closed / Lapsed |