Patent US3545313A successfully refreshed from Google Patents.
Patent US5043677A successfully refreshed from Google Patents.
US5043677A
Expired / Lapsed
US
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Time reference signal generation system
Assignee: Texas Instruments Inc
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Filing: 1990-06-29
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Granted: 1991-08-27
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Expires: 2010-06-29
Abstract
Abstract A reference time signal generation system 10 is provided which comprises a phase lock loop circuit 12 which generates a reference voltage V m . The phase lock loop circuit 12 comprises first and second divider circuits 14 and 18 coupled to the input of a phase comparator 16. The output of the phase comparator 16 is coupled to a loop filter 20 which generates a DC representation of the phase differential of the inputs of the phase comparator 16. The output of the loop filter 20 is input into a bias generator 26. The output of the bias generator 26 is coupled to the input of a voltage controlled oscillator 28 which has its output coupled to the input of second divider circuit 18. The reference voltage signal V m is taken from the output of the bias generator 26 and is transmitted to remote timing elements 32, 34 and 36 where it may be used to create reference timing signals which will accurately track the reference clock signal input into phase lock loop circuit 12.
Inventors
- 👤 Stephen R. Tomassetti
- 👤 Alan T. Wetzel
- 👤 Khodor S. Elnashar
- 👤 Rich A. Rochelle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:14
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03K; H03K3/00; H03K3/02; H03K3/023; H03K3/0231; H03L7/085
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
212 words
A circuit for providing timing signals in an integrated circuit coupled to an external clock signal, comprising: a phase lock loop circuit operable to receive the external clock signal and generate an analog reference voltage signal representative of the external clock signal, wherein said phase lock loop comprises: a phase comparator having first and second inputs and an output, said first phase comparator input coupled to the external clock signal; a loop filter having an input and an output, said loop filter coupled to said phase comparator output, said loop filter operable to receive a phase differential signal from said phase comparator and output a DC voltage signal; a bias generator circuit having an input and an output, said bias generator input coupled to said loop filter output, said bias generator circuit operable to receive said DC voltage signal and output said analog reference voltage signal; and a voltage controlled oscillator having an input coupled to said reference voltage signal and an output coupled to said second phase comparator input, said voltage controlled oscillator operable to generate a feedback signal to be input into said phase comparator circuit; and a remote timing circuit coupled to said reference voltage signal operable to generate a digital timing signal responsive to said reference voltage signal.
Claim 2
Dependent Claim
212 words
A circuit for providing timing signals in an integrated circuit coupled to an external clock signal, comprising: a phase lock loop circuit operable to receive the external clock signal and generate an analog reference voltage signal representative of the external clock signal, wherein said phase lock loop comprises: a phase comparator having first and second inputs and an output, said first phase comparator input coupled to the external clock signal; a loop filter having an input and an output, said loop filter coupled to said phase comparator output, said loop filter operable to receive a phase differential signal from said phase comparator and output a DC voltage signal; a bias generator circuit having an input and an output, said bias generator input coupled to said loop filter output, said bias generator circuit operable to receive said DC voltage signal and output said analog reference voltage signal; and a voltage controlled oscillator having an input coupled to said reference voltage signal and an output coupled to said second phase comparator input, said voltage controlled oscillator operable to generate a feedback signal to be input into said phase comparator circuit; and a remote timing circuit coupled to said reference voltage signal operable to generate a digital timing signal responsive to said reference voltage signal.
Claim 3
Dependent Claim
14 words
The circuit of claim 1 wherein said phase comparator circuit comprises an exclusive-OR gate.
Claim 4
Dependent Claim
34 words
The circuit of claim 1 wherein said loop filter comprises: a resistor coupled between said loop filter input and output; and a capacitor coupled between said loop filter output and a predetermined voltage level.
Claim 5
Dependent Claim
24 words
The circuit of claim 1 wherein said voltage controlled oscillator comprises a reference capacitor and wherein said remote timing circuit comprises a remote capacitor.
Claim 6
Dependent Claim
38 words
The circuit of claim 4 wherein said reference capacitor and said remote capacitor are formed using substantially identical processes such that said capacitors will react equivalently to variances in ambient operating conditions and to variances in said processes.
Claim 7
Dependent Claim
83 words
The circuit of claim 1 wherein said phase lock loop circuit further comprises: a first divider circuit having an input coupled to the external clock signal and an output coupled to said first phase comparator input; and a second divider circuit having an input coupled said voltage controlled oscillator output and an output coupled to said second phase comparator input, said first and second divider circuits operable to generate signals to be input into said phase comparator having substantially identical frequencies and waveforms.
Claim 8
Dependent Claim
40 words
The circuit of claim 1 wherein said voltage controlled oscillator comprises a reference dependent current source coupled to said reference voltage signal and wherein said remote timing circuit comprises a remote dependent current source coupled to said reference voltage signal.
Claim 9
Dependent Claim
42 words
The circuit of claim 7 wherein said reference dependent current source and said remote dependent current source are formed using substantially identical processes such that said current sources will react equivalently to variances in ambient operating conditions and variances in said processes.
Claim 10
Dependent Claim
40 words
The circuit of claim 1 wherein said voltage controlled oscillator comprises a reference comparator circuit coupled to a first predetermined voltage level and wherein said remote timing circuit comprises a remote comparator circuit coupled to a second predetermined voltage level.
Claim 11
Dependent Claim
39 words
The circuit of claim 9 wherein said reference comparator circuit and said remote comparator circuit are formed using substantially identical processes such that said comparators will react equivalently to variances in ambient operating conditions and variances in said processes.
Claim 12
Dependent Claim
36 words
The circuit of claim 10 wherein said second predetermined voltage level is selectively sized relative to said first predetermined voltage level such that said digital timing signal is selectively sized relative to the external clock signal.
Claim 13
Dependent Claim
208 words
An integrated circuit coupled to an external clock signal, comprising: a phase lock loop circuit operable to receive the external clock signal and generate an analog reference voltage signal representative of the external clock signal, said phase lock loop circuit comprising: a phase comparator having first and second inputs and an output, said first phase comparator input coupled to the external clock signal; a loop filter having an input and an output, said loop filter input coupled to said phase comparator output, said loop filter operable to receive a phase differential signal from said phase comparator and output a DC voltage signal; a bias generator circuit having an input and an output, said bias generator input coupled to said loop filter output, said bias generator circuit operable to receive said DC voltage signal and output said analog reference voltage signal; and a voltage controlled oscillator having an input coupled to said reference voltage signal and an output coupled to said second phase comparator input, said voltage controlled oscillator operable to generate a feed back signal to be input into said phase comparator circuit; and a remote timing circuit coupled to said reference voltage signal and operable to generate a digital timing signal responsive to said reference voltage signal.
Claim 14
Dependent Claim
208 words
An integrated circuit coupled to an external clock signal, comprising: a phase lock loop circuit operable to receive the external clock signal and generate an analog reference voltage signal representative of the external clock signal, said phase lock loop circuit comprising: a phase comparator having first and second inputs and an output, said first phase comparator input coupled to the external clock signal; a loop filter having an input and an output, said loop filter input coupled to said phase comparator output, said loop filter operable to receive a phase differential signal from said phase comparator and output a DC voltage signal; a bias generator circuit having an input and an output, said bias generator input coupled to said loop filter output, said bias generator circuit operable to receive said DC voltage signal and output said analog reference voltage signal; and a voltage controlled oscillator having an input coupled to said reference voltage signal and an output coupled to said second phase comparator input, said voltage controlled oscillator operable to generate a feed back signal to be input into said phase comparator circuit; and a remote timing circuit coupled to said reference voltage signal and operable to generate a digital timing signal responsive to said reference voltage signal.
Claim 15
Dependent Claim
14 words
The circuit of claim 12 wherein said phase comparator circuit comprises an exclusive-OR gate.
Claim 16
Dependent Claim
34 words
The circuit of claim 12 wherein said loop filter comprises: a resistor coupled between said loop filter input and output; and a capacitor coupled between said loop filter output and a predetermined voltage level.
Claim 17
Dependent Claim
24 words
The circuit of claim 12 wherein said voltage controlled oscillator comprises a reference capacitor and wherein said remote timing circuit comprises a remote capacitor.
Claim 18
Dependent Claim
40 words
The circuit of claim 15 wherein said reference capacitor and said remote capacitor are formed using substantially identical processes such that said capacitors will react equivalently to variances in ambient operating conditions affecting the circuit and variances in said processes.
Claim 19
Dependent Claim
84 words
The circuit of claim 12 wherein said phase lock loop circuit further comprises: a first divider circuit having an input coupled to the external clock signal and an output coupled to said first phase comparator input; and a second divider circuit having an input coupled to said voltage controlled oscillator output and an output coupled to said second phase comparator input, said first and second divider circuits operable to generate signals to be input into said phase comparator having substantially identical frequencies and waveforms.
Claim 20
Dependent Claim
40 words
The circuit of claim 12 wherein said voltage controlled oscillator comprises a reference dependent current source coupled to said reference voltage signal and wherein said remote timing circuit comprises a remote dependent current source coupled to said reference voltage signal.
Claim 21
Dependent Claim
42 words
The circuit of claim 18 wherein said reference dependent current source and said remote dependent current source are formed using substantially identical processes such that said current sources will react equivalently to variances in ambient operating conditions and variances in said processes.
Claim 22
Dependent Claim
40 words
The circuit of claim 12 wherein said voltage controlled oscillator comprises a reference comparator circuit coupled to a first predetermined voltage level and wherein said remote timing circuit comprises a remote comparator circuit coupled to a second predetermined voltage level.
Claim 23
Dependent Claim
39 words
The circuit of claim 20 wherein said reference comparator circuit and said remote comparator circuit are formed using substantially identical processes such that said comparators will react equivalently to variances in ambient operating conditions and variances in said processes.
Claim 24
Dependent Claim
36 words
The circuit of claim 21 wherein said second predetermined voltage level is selectively sized relative to said first predetermined voltage level such that said digital timing signal is selectively sized relative to the external clock signal.
Claim 25
Independent Claim
171 words
A method for providing timing signals in an integrated circuit coupled to an external clock signal, comprising the steps of: generating a reference voltage signal using a phase lock loop circuit coupled to the external clock signal and resident in the integrated circuit, the reference voltage signal comprising an analog representation of the external clock signal, the external clock signal comprising a digital signal, comprising the steps of: generating a feedback signal using a voltage controlled oscillator coupled to the reference voltage signal; comparing the phase of the external clock signal with the feedback signal to generate a series of digital pulses; converting the series of digital pulses into an analog voltage signal using a loop filter circuit; and biasing the analog voltage signal to generate the reference voltage signal; transmitting the reference voltage signal to a remote timing element resident in the integrated circuit; and generating a digital timing signal in the remote timing element selectively synchronized with the external clock signal responsive to the receipt of the reference voltage.
Claim 26
Independent Claim
171 words
A method for providing timing signals in an integrated circuit coupled to an external clock signal, comprising the steps of: generating a reference voltage signal using a phase lock loop circuit coupled to the external clock signal and resident in the integrated circuit, the reference voltage signal comprising an analog representation of the external clock signal, the external clock signal comprising a digital signal, comprising the steps of: generating a feedback signal using a voltage controlled oscillator coupled to the reference voltage signal; comparing the phase of the external clock signal with the feedback signal to generate a series of digital pulses; converting the series of digital pulses into an analog voltage signal using a loop filter circuit; and biasing the analog voltage signal to generate the reference voltage signal; transmitting the reference voltage signal to a remote timing element resident in the integrated circuit; and generating a digital timing signal in the remote timing element selectively synchronized with the external clock signal responsive to the receipt of the reference voltage.
Claim 27
Dependent Claim
46 words
The method of claim 23 wherein said step of generating a reference voltage comprises the step of: shaping the signals of the external clock signal and the feedback signal prior to said step of comparing such that the signals have substantially identical waveforms and duty cycles.
Claim 28
Dependent Claim
24 words
The method of claim 23 wherein said step of generating a feedback signal comprises the step of repeatedly charging and discharging a reference capacitor.
Claim 29
Dependent Claim
39 words
The method of claim 25 wherein said step of generating a digital timing signal comprises the step of charging a remote capacitor resident in the remote timing element, the remote capacitor proportionally sized with respect to the reference capacitor.
References Cited (Backward Citations)
US4667168A
Cited
US4904955A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-26 | 1995-02-25 | 1995-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-26 | 1999-02-25 | 1999-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-26 | 2003-02-25 | 2003-08-27 | $7700.00 | Window Closed / Lapsed |