US5043655A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current sensing buffer for digital signal line testing
Assignee: Fluke Corp
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Filing: 1989-03-14
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Granted: 1991-08-27
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Expires: 2009-03-14
Abstract
Abstract A current sensing buffer 26 for driving a digital signal line of a unit under test 12 is composed of current mirror circuits in series with output switching transistors supplying test signals to the digital signal line. The current mirror circuits 66, 72 and 80, 84 generate sample currents corresponding to the magnitude of current through the respective drivers 68 and 78 to detect drive faults caused by bus or component failures. In buses comprised of several digital signal lines, one current sensing buffer 26 is used per line, and each curent sensing buffer 26 is controlled by a programmable circuit tester 10. The current sensing buffer 26 can be incorporated into an interface pod 14 which is substituted for a control component of a unit under test 12.
Inventors
- 👤 John M. Anholm, Jr.
- 👤 Gerald J. McMorrow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 06:28
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/0092
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
85 words
A current sensing buffer for use in testing an electrical data signal line, comprising: state switching means for generating signals having predetermined logic levels; current sensing means including a current mirror circuit for transmitting said predetermined logic level signals from said state switching means to said data signal line and for measuring current levels corresponding thereto; and fault detection means for comparing measured current levels measured by said current sensing means to predetermined acceptable ranges of current levels and, in response, outputting an error signal.
Claim 2
Dependent Claim
85 words
A current sensing buffer for use in testing an electrical data signal line, comprising: state switching means for generating signals having predetermined logic levels; current sensing means including a current mirror circuit for transmitting said predetermined logic level signals from said state switching means to said data signal line and for measuring current levels corresponding thereto; and fault detection means for comparing measured current levels measured by said current sensing means to predetermined acceptable ranges of current levels and, in response, outputting an error signal.
Claim 3
Dependent Claim
27 words
A current sensing buffer in accordance with claim 1, wherein said state switching means includes means for storing and selecting said predetermined logic levels to be generated.
Claim 4
Dependent Claim
64 words
A current sensing buffer in accordance with claim 1, further comprising tri-stating protection means responsive to said fault detection means error signal for controlling said state switching means for generating selectively (a) said predetermined logic levels and (b) a high impedance output through said current sensing means to said bus for protecting said current sensing buffer and components coupled to said data signal line.
Claim 5
Dependent Claim
102 words
A current sensing buffer for testing a digital signal line, comprising: signal generator means for outputting test signals of predetermined logic level signals; line driver means for supplying said predetermined logic level signals from said signal generator means to said digital signal line and for measuring corresponding current levels of said logic level signals transmitted to said digital signal line, said line driver means including a current mirror circuit for providing sample output signals corresponding to said current levels; and error detecting means for comparing said sample output signals to corresponding predetermined acceptable current level and, in response, generating an error signal.
Claim 6
Dependent Claim
102 words
A current sensing buffer for testing a digital signal line, comprising: signal generator means for outputting test signals of predetermined logic level signals; line driver means for supplying said predetermined logic level signals from said signal generator means to said digital signal line and for measuring corresponding current levels of said logic level signals transmitted to said digital signal line, said line driver means including a current mirror circuit for providing sample output signals corresponding to said current levels; and error detecting means for comparing said sample output signals to corresponding predetermined acceptable current level and, in response, generating an error signal.
Claim 7
Dependent Claim
62 words
The current sensing buffer of claim 4, wherein said signal generator means includes means to generate positive and negative logic level signals and wherein said current mirror circuit includes corresponding positive and negative logic level current mirror driver circuits for measuring and supplying said respective positive and negative logic level signals supplied by said signal generator means to said digital signal line.
Claim 8
Dependent Claim
59 words
The current sensing buffer according to claim 4, wherein said line driver means includes tri-stating means responsive to said error signal for selectively supplying (a) said predetermined logic levels from said signal generator means and (b) a high impedance output to said digital signal line for protecting said current sensing buffer and components coupled to said digital signal line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-26 | 1995-02-25 | 1995-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-26 | 1999-02-25 | 1999-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-26 | 2003-02-25 | 2003-08-27 | $7700.00 | Window Closed / Lapsed |