Chip package capacitor cover

Claim 2

A cover for a semiconductor chip package, comprising: as) a cover plate; b) sealing surface means located on a surface of the cover plate for providing a seal between the cover plate and the package; and c) mounting surface means located on a capacitor mounted surface of the cover plate for mounting a capacitor to the capacitor mounting surface of the cove plate, the mounting surface means comprising metalization means including a metalized power pad and a metalized ground pad for mounting a capacitor on the capacitor mounting surface of the cover plate.

Claim 3

The cover of claim 1 wherein the metalization means comprises a power plane and a ground plane, both planes being integral to the cover plate.

Claim 4

The cover of claim 2 wherein the metalization means comprises: a) vias for connecting the metalized power pad to the integral power plane and for connecting the integral power plane to a semiconductor chip package power connection; and b) vias for connecting the metalized ground pad to the integral ground plane and for connecting the integral ground plane to a semiconductor chip package ground connection.

Claim 5

The cover of claim 2 wherein the metalization means comprises: a) castellations for connecting the metalized power pad to the integral power plane and for connecting the integral power plane to a semiconductor chip package power connection; and b) castellations for connecting the metalized ground pad to the integral ground plane and for connecting the integral ground plane to a semiconductor chip package ground connection.

Claim 6

The cover of claim 2 wherein the metalization means comprises: a) metal clips for connecting the metalized power pad to the integral power plane and for connecting the integral power plane to a semiconductor chip package power connection; and b) metal clips for connecting the metalized ground pad to the integral ground plane and for connecting the integral ground plane to a semiconductor chip package ground connection.

Claim 7

A cover for a semiconductor chip package comprising: a) a cover plate; b) sealing surface means located on a surface of the cover plate for providing a seal between the cover plate and the package; c) mounting surface means located on a capacitor mounting surface of the cover plate for mounting a plurality of capacitors on the capacitor mounting surface of the cover plate, the mounting surface means including metalization means comprising metalized power pad regions and metalized ground pad regions; d) the metalized power pad regions being electrically isolated form the metalized ground pad regions and being configured for connection to semiconductor chip package power connections; and e) the metalized ground pad regions being electrically isolated from the metalized power pad regions and being configured for connection to semiconductor chip package ground connections.

Claim 8

A cover for a semiconductor chip package comprising: a) a cover plate; b) sealing surface means located on a surface of the cover plate for providing a seal between the cover plate and the package; c) mounting surface means located on a capacitor mounting surface of the cover plate for mounting a plurality of capacitors on the capacitor mounting surface of the cover plate, the mounting surface means including metalization means comprising metalized power pad regions and metalized ground pad regions; d) the metalized power pad regions being electrically isolated form the metalized ground pad regions and being configured for connection to semiconductor chip package power connections; and e) the metalized ground pad regions being electrically isolated from the metalized power pad regions and being configured for connection to semiconductor chip package ground connections.

Claim 9

The cover of claim 6 wherein the metalization means comprises a power plane and a ground plane, both paleness being integral to the cover plate.

Claim 10

The cover of claim 7 wherein the metalization means comprises: a) vias for connecting the metalized power pad regions to the integral power plane and for connecting the integral power plane to a semiconductor chip package power connection; and b) vias for connecting the metalized ground pad regions to the integral ground plane and for connecting the integral ground plane to a semiconductor chip package ground connection.

Claim 11

The cover of claim 7 wherein the metalization means comprises: a) castellations for connecting the metalized power pads to the integral power plane and for connecting the integral power plane to a semiconductor chip package power connection; and b) castellations for connecting the metalized ground pads to the integral ground plane and for connecting the integral ground plane to semiconductor chip package ground connection.

Claim 12

The cover of claim 7 wherein the metalization means comprises: a) metal clips for connecting the metalized power pads to the integral power plane and for connecting the integral power plane to a semiconductor chip package power connection; and b) metal clips for connecting the metalized ground pads to the integral ground plane and for connecting the integral ground plane to a semiconductor chip package ground connection.

Claim 13

A semiconductor chip package, comprising: a) package means for holding a semiconductor chip; b) a cover plate for providing a package seal, the cover plate comprising sealing surface means for providing a seal between the cover plate and the package means; and c) mounting surface means located on a capacitor mounting surface of the cover plate for mounting a capacitor to the capacitor mounting surface of the cover plate, the mounting surface means including metalization means comprising a metalized power pad and a metalized ground pad for electrically connecting the capacitor to the capacitor mounting surface of the cover plate.

Claim 14

A semiconductor chip package, comprising: a) package means for holding a semiconductor chip; b) a cover plate for providing a package seal, the cover plate comprising sealing surface means for providing a seal between the cover plate and the package means; and c) mounting surface means located on a capacitor mounting surface of the cover plate for mounting a capacitor to the capacitor mounting surface of the cover plate, the mounting surface means including metalization means comprising a metalized power pad and a metalized ground pad for electrically connecting the capacitor to the capacitor mounting surface of the cover plate.

Claim 15

The semiconductor chip package of claim 11 wherein the metalization means comprises a power plane and a ground plane, both planes being integral to the cover plate.

Claim 16

The semiconductor chip package of claim 12 wherein the metalization means comprises: a) vias for connecting the metalized power pad to the integral power plane and for connecting the integral power plane to a power connection of the semiconductor chip package; and b) vias for connecting the metalized ground pad to the integral ground plane and for connecting the integral ground plane to a ground connection of the semiconductor chip package.

Claim 17

The semiconductor chip package of claim 12 wherein the metalization means comprises: a) castellations for connecting the metalized power pad to the integral power plane and for connecting the integral power plane to a power connection of the semiconductor chip package; and b) castellations for connecting the metalized ground pad to the integral ground plane and for connecting the integral ground plane to a ground connection of the semiconductor chip package.

Claim 18

The semiconductor chip package of claim 12 wherein the metalization means comprises: a) metal clips for connecting the metalized power pad to the integral power plane and for connecting the integral power plane to a power connection of the semiconductor chip package; and b) metal clips for connecting the metalized ground pad to the integral ground plane and for connecting the integral ground plane to a ground connection of the semiconductor chip package.

Claim 19

A semiconductor chip package, comprising: a) package means for holding a semiconductor chip; b) a cover plate for providing a package seal, the cover plate comprising sealing surface means for providing a seal between the cove plate and thepackage means; c) mounting surface means located on a capacitor mounting surface of the cover plate for mounting a plurality of capacitors on the capacitor mounting surface of the cover plate, the mounting surface means including metalization mean comprising metalized power pad regions and metalized ground pad regions; d) the metalized power pad regions being electrically isolated for the metalized ground pad regions and being configured for connection to semiconductor chip package power connections; and e) the metalized ground pad regions being electrically isolated from eh metalized power pad regions and being configured for connection semiconductor chip package ground connections.

Claim 20

A semiconductor chip package, comprising: a) package means for holding a semiconductor chip; b) a cover plate for providing a package seal, the cover plate comprising sealing surface means for providing a seal between the cove plate and thepackage means; c) mounting surface means located on a capacitor mounting surface of the cover plate for mounting a plurality of capacitors on the capacitor mounting surface of the cover plate, the mounting surface means including metalization mean comprising metalized power pad regions and metalized ground pad regions; d) the metalized power pad regions being electrically isolated for the metalized ground pad regions and being configured for connection to semiconductor chip package power connections; and e) the metalized ground pad regions being electrically isolated from eh metalized power pad regions and being configured for connection semiconductor chip package ground connections.

Claim 21

The package of claim 16 wherein the metalization means comprises a power plane and a ground plane, both planes being integral to the cover plate.

Claim 22

The semiconductor chip package of claim 17 wherein the metalization means comprises: a) vias for connecting the metalized power pad regions to the integral power plane and for connecting the integral power plane to semiconductor chip package power connections; and b) vias for connecting the metalized ground pad regions to the integral ground plane and for connecting the integral ground plane to semiconductor chip package ground connections.

Claim 23

The semiconductor chip package of claim 17 wherein the metalization means comprises: a) castellations for connecting the metalized power pads to the integral power plane and for connecting the integral power plane to semiconductor chip package power connections; and b) castellations for connecting the metalized ground pads to the integral ground plane and for connecting the integral ground plane to semiconductor chip package ground connections.

Claim 24

The semiconductor chip package of claim 17 wherein the metalization means comprises: a) metal clips for connecting the metalized power pads to the integral power plane and for connecting the integral power plane to a semiconductor chip package power connection; and b) metal clips for connecting the metalized ground pads to the integral ground plane and for connecting the integral ground plane to semiconductor chip package ground connections.