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US5041886A
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Nonvolatile semiconductor memory device and manufacturing method thereof
Assignee: Samsung Electronics Co Ltd
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Filing: 1989-09-25
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Granted: 1991-08-20
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Expires: 2009-09-25
Abstract
Abstract A nonvolatile semiconductor memory device is provided including a doped semiconductor substrate and three gate conductor layers electrically insulated from each other in the cell area on the substrate. A first floating gate conductor layer is formed on the substrate and covered by a second control gate conductor layer, forming a twofold polycrystalline silicon structure. A third select gate conductor layer is formed along one side wall of the twofold structure of the floating gate and control gate conductor layers, having a side wall spacer structure. The first conductor layer serves as a floating gate; the second conductor layer serves as a control gate; and the third conductor layer serves as a select gate. A field oxide layer is provided to separate cells from each other. The control and the select gates are connected in a region between cells through the field oxide layer. By providing the third conductor in the form of a side wall spacer, the cell area can be greatly reduced.
Inventors
- 👤 Soo-Cheol Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:07
CPC Classifications
H; H10; H10B; H10B41/00; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0425; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/6891; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/0133; H10D64/031; H10D64/035; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D64/60; H10D64/66; H10D64/671; H10W; H10W20/00; H10W20/01; H10W20/071
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
110 words
A nonvolatile semiconductor memory device including a plurality of memory cells, comprising: a silicon substrate doped with an impurity; a group of electrically insulated gate conductors on said substrate including: a first gate conductor provided as a floating gate; a second gate conductor provided as a control gate and covering said first gate conductor; and a third gate conductor provided as a select gate; said third gate conductor being formed along a side wall of the first and second gate conductors as a side wall spacer; said second and third gate conductors being connected via a gate contact hole which is formed on a field oxide layer between memory cells.
Claim 2
Dependent Claim
110 words
A nonvolatile semiconductor memory device including a plurality of memory cells, comprising: a silicon substrate doped with an impurity; a group of electrically insulated gate conductors on said substrate including: a first gate conductor provided as a floating gate; a second gate conductor provided as a control gate and covering said first gate conductor; and a third gate conductor provided as a select gate; said third gate conductor being formed along a side wall of the first and second gate conductors as a side wall spacer; said second and third gate conductors being connected via a gate contact hole which is formed on a field oxide layer between memory cells.
Claim 3
Dependent Claim
30 words
A nonvolatile semiconductor memory device according to claim 1, wherein a gate contact hole is provided in each of a plurality of groups of a predetermined number of memory cells.
Claim 4
Dependent Claim
21 words
A nonvolatile semiconductor memory device according to claim 2, wherein said first, second and third conductors are formed with polycrystalline silicon.
Claim 5
Dependent Claim
180 words
A non-volatile semiconductor memory device comprising: a doped substrate; a first conductor layer formed on said substrate, including a plurality of portions each constituting a respective floating gate for a corresponding memory cell; a second conductor layer formed on said substrate and covering said first conductor layer, including a plurality of portions each constituting a respective control gate for a corresponding memory cell; each said control gate covers a corresponding floating gate of the same memory cell; a third conductor layer formed on said substrate and having the structure of a side wall spacer along one side wall of the twofold structure of the first and second conductor layers, including a plurality of portions each constituting a select gate for a memory cell; each said select gate being positioned along one side wall of the twofold structure of the floating gate and control gate of the same memory cell; said first, second, and third conductors are insulated from each other in the memory cell regions, and said second and third conductors are connected in an area in between memory cells.
Claim 6
Dependent Claim
180 words
A non-volatile semiconductor memory device comprising: a doped substrate; a first conductor layer formed on said substrate, including a plurality of portions each constituting a respective floating gate for a corresponding memory cell; a second conductor layer formed on said substrate and covering said first conductor layer, including a plurality of portions each constituting a respective control gate for a corresponding memory cell; each said control gate covers a corresponding floating gate of the same memory cell; a third conductor layer formed on said substrate and having the structure of a side wall spacer along one side wall of the twofold structure of the first and second conductor layers, including a plurality of portions each constituting a select gate for a memory cell; each said select gate being positioned along one side wall of the twofold structure of the floating gate and control gate of the same memory cell; said first, second, and third conductors are insulated from each other in the memory cell regions, and said second and third conductors are connected in an area in between memory cells.
Claim 7
Dependent Claim
44 words
A memory device as recited in claim 4, wherein: the memory cells are separated from each other by a field oxide layer; and said connection between the second and third conductor layer includes a connection through a contact hole in said field oxide layer.
Claim 8
Dependent Claim
60 words
A memory device as recited in claim 4, wherein: the memory cells are separated from each other by a field oxide layer; said connection between the second and third conductor layer includes a plurality of connections each being located in between memory cells; and each said plurality of connections being through a corresponding contact hole in said field oxide layer.
Claim 9
Dependent Claim
22 words
A memory device as recited in claim 4, wherein: each said first, second, and third conductor layer is formed of polycrystalline silicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-19 | 1995-02-18 | 1995-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-19 | 1999-02-18 | 1999-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-19 | 2003-02-18 | 2003-08-20 | $7700.00 | Window Closed / Lapsed |