Heterojunction bipolar transistor

Claim 2

A heterojunction bipolar transistor comprising: a substrate; a collector layer formed on the substrate; a base layer formed on the collector layer; and an emitter layer made of InP having a band gap larger than that of the base layer, said emitter layer formed on the base layer and including a region extending from inside of the emitter layer to inside of the base layer, said region having a composition which varies in such a manner that a band gap is gradually decreased toward a base/collector junction, the base layer and a part of the emitter layer being made of GaInAsP whose composition is determined such that the base layer and the part of the emitter layer are lattice matched with InP and that a composition ratio β of P to As in a base/emitter junction satisfies an inequality relationship 0.3≦β≦0.7.

Claim 3

A heterojunction bipolar transistor as set forth in claim 1, wherein said composition ratio β of P to As is 0.5.

Claim 4

A heterojunction bipolar transistor as set forth in claim 1, wherein said collector layer of said heterojunction bipolar transistor includes an n - type InP layer and an n - type Ga 0 .47(1-β) In 0 .53+0.47 β As 1- β P.sub.β graded composition layer (1≧β≧0), and said base layer of the transistor includes a p + type Ga 0 .47(1-β) In 0 .53+0.47 β As 1- β P.sub.β graded composition layer having a varying composition ratio β starting from 0.

Claim 5

A heterojunction bipolar transistor as set forth in claim 1, wherein said collector layer of said heterojunction bipolar transistor comprises an i type InP layer.

Claim 6

A heterojunction bipolar transistor as set forth in claim 1, wherein said collector layer of said heterojunction bipolar transistor comprises a p - type InP layer.

Claim 7

A heterojunction bipolar transistor as set forth in claim 1, wherein said collector layer of said heterojunction bipolar transistor comprises an n - type Ga 0 .47 In 0 .53 As layer.

Claim 8

A heterojunction bipolar transistor as set forth in claim 1, wherein said collector layer of said heterojunction bipolar transistor comprises a p - type Ga 0 .47 In 0 .53 As layer.

Claim 9

A heterojunction bipolar transistor as set forth in claim 1, wherein said collector layer of said heterojunction bipolar transistor comprises an i type Ga 0 .47 In 0 .53 As layer.

Claim 10

A heterojunction bipolar transistor as set forth in claim 1, wherein said collector layer of said heterojunction bipolar transistor includes an n - type InP layer and an n - type Ga 0 .47(1-β) In 0 .53+0.47 β As 1- β P.sub.β graded composition layer (1≧β≧0), said base layer of the transistor comprises a p + type Ga 0 .47(1-β) In 0 .53+0.47β As 1- β P.sub.β graded composition layer (0≦β≦0.5), and said emitter layer of the transistor includes an n type Ga 0 .47(1-β) In 0 .53+0.47β As 1- β P.sub.β graded composition layer (0.5≦β≦1.0) and an n type InP layer.

Claim 11

A heterojunction bipolar transistor as set forth in claim 1, wherein said heterojunction bipolar transistor comprises an n + type InP layer as its collector contact layer formed on a semi-insulating InP substrate, an n - type InP layer and an n - type Ga 0 .47(1-β) In 0 .53+0.47β As 1- β P.sub.β layer (1≧β≧0) as its collector layers sequentially formed on said collector contact layer, a p + type Ga 0 .47(1-β) In 0 .53+0.47β As 1- β P.sub.β layer (0≦β≦0.5) as its base layer, an n type Ga 0 .47(1-β) In 0 .53+0.47β As 1- β P.sub.β layer (0.5≦β≦1.0) and an n type InP layer and an n type Ga 0 .47(1-β) In 0 .53+0.47β As 1- β P.sub.β layer (1.0≧β≧0) which form its emitter layer, and an n + type Ga 0 .47 In 0 .53 As layer as its emitter cap layer.

Claim 12

A heterojunction bipolar transistor as set forth in claim 1, wherein said heterojunction bipolar transistor has a collector top structure of said emitter, base and collector layers sequentially formed on said substrate.

Claim 13

A heterojunction bipolar transistor as set forth in claim 1, wherein said heterojunction bipolar transistor comprises an Au layer as its collector electrode, a Cr/Au layer as its base electrode and a GeAu/Au layer as its emitter electrode.

Claim 14

A heterojunction bipolar transistor integrate circuit comprising: a substrate; a collector layer formed on the substrate; a base layer formed on the collector layer; and an emitter layer made of InP having a band gap larger than that of the base layer, said emitter layer formed on the base layer and including a region extending from inside of the emitter layer to inside of the base layer, said region having a composition which varies in such a manner that a band gap is gradually decreased toward a base/collector junction, the base layer and a part of the emitter layer being made of GaInAsP whose composition is determined such that the base layer and the part of the emitter layer are lattice matched with InP composition and that a composition ratio β of P to As in a base/emitter junction satisfies an inequality relationship 0.3≦β≦0.7.

Claim 15

A heterojunction bipolar transistor integrate circuit comprising: a substrate; a collector layer formed on the substrate; a base layer formed on the collector layer; and an emitter layer made of InP having a band gap larger than that of the base layer, said emitter layer formed on the base layer and including a region extending from inside of the emitter layer to inside of the base layer, said region having a composition which varies in such a manner that a band gap is gradually decreased toward a base/collector junction, the base layer and a part of the emitter layer being made of GaInAsP whose composition is determined such that the base layer and the part of the emitter layer are lattice matched with InP composition and that a composition ratio β of P to As in a base/emitter junction satisfies an inequality relationship 0.3≦β≦0.7.

Claim 16

A heterojunction bipolar transistor integrated circuit as set forth in claim 13, wherein said composition ratio β of P to As is 0.5.

Claim 17

A heterojunction bipolar transistor integrated circuit as set forth in claim 13, wherein an InP semiconductor laser device is integrated on said substrate.