Time division speech path apparatus

Claim 1

A time division speech path apparatus, having time division highways with input highways having different frame phrases, for performing time division switching between time slots of the input highways and output highways, the apparatus comprising: a multiplexer for the time division highways; a speech path memory connected to said multiplexer; a speech path control memory; a frame synchronization detector connected to the input highways for detecting frame positions, also called highway frame phases herein, on data formats of the respective input highways and synchronizing byte phase divisions between the input highways, each of the data formats being constituted by a pointer consisting of at least one byte representing a time slot position at which a first channel of user data on a corresponding one of the time division highways is stored, and a plurality of time slots for carrying a plurality of user data; a pointer detector connected to said frame synchronization detector for holding a difference between a highway frame phase from said frame synchronization detector and a system frame phase of said speech path independent of a frame phase of the input highways to which a system of said speech path is internally generated or externally supplied and a pointer value read out from contents of the pointer of each of said input highways; a pointer inserting circuit for writing pointer values in pointers on said output and input highways; an address converter connected to said pointer detector and also connected to said speech path control memory for converting sequential addresses sequentially generated in accordance with the system frame phase, into data on the basis of detected frame phrases and pointer values, and outputting the data as addresses for said speech path control memory; a selector for selecting data, which are read out from said speech path control memory by using the outputs from said address converter as addresses, during a write mode of said speech path memory so as to provide the data as addresses to said speech path memory, sequentially writing data obtained by multiplexing data from said input highways in said speech path memory in accordance with the addresses, and selecting sequential addresses, which are sequentially generated by a counter in accordance with a frame phase independent of the system frame phase, during a read mode of said speech path memory so as to provide the sequential addresses to said speech path memory as addresses; and a demultiplexer for sequentially reading out contents from said speech path memory, demultiplexing the read contents, and outputting the demultiplexed data to said output highways.