Time division switching for multi-channel calls using two time switch memories acting as a frame aligner

Claim 2

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting an incoming frame having time slots in which signals of said multi-channel calls are carried; an outgoing highway for supporting an outgoing frame having time slots in which corresponding signals of said multi-channels calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; phase detector means for detecting a phase difference between said incoming and outgoing frames; and control means for writing signals on said incoming highway into one of said first and second time switch memories and reading signals from the other time switch memory into specified time slots of said outgoing highway in accordance with said phase difference and control data specifying addresses of said first and second time switch memories so that the beginning of said outgoing frame coincides with the one of said time slots of said incoming frame which is displaced from the beginning of said incoming frame by an amount equal to said detected phase difference.

Claim 3

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting an incoming frame having time slots in which signals of said multi-channel calls are carried; an outgoing highway for supporting an outgoing frame having time slots in which corresponding signals of said multi-channels calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector connected to said oncoming highway for detecting the beginning of said incoming frame; means for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a demultiplexer having an input terminal connected to said incoming highway and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer alternately establishing a connection between said input terminal and one of said output terminals at frame intervals in response to the presence of a most significant bit of said write address; a multiplexer having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminal connected to said outgoing highway, said multiplexer alternately establishing a connection from one of said input terminals to said output terminal at frame intervals in response to the absence of said most significant bit of said write address; a control memory having memory locations corresponding to the time slots of each of said incoming and outgoing frames; means for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; latch means for latching said read address as an indication of a phase difference between said incoming and outgoing frames in response to an output signal from said frame detector; and control means for writing a read address of said first and second time switch memories into said control memory in accordance with said latched address and a switching signal and reading signals from said first and second time switch memories in accordance with said read address of said control memory.

Claim 4

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting an incoming frame having time slots in which signals of said multi-channel calls are carried; an outgoing highway for supporting an outgoing frame having time slots in which corresponding signals of said multi-channels calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector connected to said oncoming highway for detecting the beginning of said incoming frame; means for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a demultiplexer having an input terminal connected to said incoming highway and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer alternately establishing a connection between said input terminal and one of said output terminals at frame intervals in response to the presence of a most significant bit of said write address; a multiplexer having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminal connected to said outgoing highway, said multiplexer alternately establishing a connection from one of said input terminals to said output terminal at frame intervals in response to the absence of said most significant bit of said write address; a control memory having memory locations corresponding to the time slots of each of said incoming and outgoing frames; means for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; latch means for latching said read address as an indication of a phase difference between said incoming and outgoing frames in response to an output signal from said frame detector; and control means for writing a read address of said first and second time switch memories into said control memory in accordance with said latched address and a switching signal and reading signals from said first and second time switch memories in accordance with said read address of said control memory.

Claim 5

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting an incoming frame having time slots in which signals of said multi-channel calls are carried; an outgoing highway for supporting an outgoing frame having time slots in which corresponding signals of said multi-channels calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector connected to said incoming highway for detecting the beginning of said incoming frame; means for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a control memory having memory locations corresponding to the time slots of each of said incoming and outgoing frames; means for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; a demultiplexer having an input terminal connected to said incoming highway and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer alternately establishing a connection from said input terminal to one of said output terminals in response to the presence of a most significant bit of said read address of said control memory; a multiplexer having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminal connected to said outgoing highway, said multiplexer alternately establishing a connection from one of said input terminals to said output terminal in response to the absence of said most significant bit of said read address of said control memory; latch means for latching said write address of said first and second time switch memories as an indication of a phase difference between said incoming and outgoing frames in response to said most significant bit of said read address; and control means for writing a read address of said first and second time switch memories into said control memory in accordance with said latched address and a switching signal and reading signals from said first and second time switch memories in accordance with said read address of said control memory.

Claim 6

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting an incoming frame having time slots in which signals of said multi-channel calls are carried; an outgoing highway for supporting an outgoing frame having time slots in which corresponding signals of said multi-channels calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector connected to said incoming highway for detecting the beginning of said incoming frame; means for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a control memory having memory locations corresponding to the time slots of each of said incoming and outgoing frames; means for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; a demultiplexer having an input terminal connected to said incoming highway and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer alternately establishing a connection from said input terminal to one of said output terminals in response to the presence of a most significant bit of said read address of said control memory; a multiplexer having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminal connected to said outgoing highway, said multiplexer alternately establishing a connection from one of said input terminals to said output terminal in response to the absence of said most significant bit of said read address of said control memory; latch means for latching said write address of said first and second time switch memories as an indication of a phase difference between said incoming and outgoing frames in response to said most significant bit of said read address; and control means for writing a read address of said first and second time switch memories into said control memory in accordance with said latched address and a switching signal and reading signals from said first and second time switch memories in accordance with said read address of said control memory.

Claim 7

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are carried; an outgoing highway for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channel calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each said incoming and outgoing frames; phase detector means for detecting a phase difference between said incoming and outgoing frames; and control means for (a) writing signals on said incoming highway into an alternate one of said first and second time switch memories, (b) making a decision if a time slot number of at least one signal of a given multi-channel call is greater than said phase difference and at the same time if a combined value of a time slot number of a corresponding signal on the outgoing highway and said phase difference is smaller than the highest time slot number of said incoming frames, and (c) in the absence of said decision, reading all signals of said given multi-channel call from one of said first and second time switch memories into specified time slots of a first outgoing frame which at least partially overlaps the incoming frame of said given multi-channel call in accordance with said phase difference and a switching signal and in the presence of said decision, reading all signals of said given multi-channel call from one of said time switch memories into said specified time slots of a second outgoing frame subsequent to said first outgoing frame in accordance with said phase difference and said switching signal.

Claim 8

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are carried; an outgoing highway for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channel calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each said incoming and outgoing frames; phase detector means for detecting a phase difference between said incoming and outgoing frames; and control means for (a) writing signals on said incoming highway into an alternate one of said first and second time switch memories, (b) making a decision if a time slot number of at least one signal of a given multi-channel call is greater than said phase difference and at the same time if a combined value of a time slot number of a corresponding signal on the outgoing highway and said phase difference is smaller than the highest time slot number of said incoming frames, and (c) in the absence of said decision, reading all signals of said given multi-channel call from one of said first and second time switch memories into specified time slots of a first outgoing frame which at least partially overlaps the incoming frame of said given multi-channel call in accordance with said phase difference and a switching signal and in the presence of said decision, reading all signals of said given multi-channel call from one of said time switch memories into said specified time slots of a second outgoing frame subsequent to said first outgoing frame in accordance with said phase difference and said switching signal.

Claim 9

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are carried; an outgoing highway for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channels calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector connected to said incoming highway for detecting the beginning of said incoming frame; means for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a demultiplexer having an input terminal connected to said incoming highway and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer alternately establishing a connection from said incoming highway to one of said first and second output terminals in response to a most significant bit of said write address; a control memory having first and second memory locations corresponding to the time slots of each of said incoming and outgoing frames; means for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; latch means for latching said read address as an indication of a phase difference between said incoming and outgoing frames in response to an output signal from said frame detector; and control means responsive to said latched address and to a time slot interchanging relationship between said incoming and outgoing highways for (a 1 ) writing a read address of said first and second time switch memories into said first memory locations of said control memory, (a 2 ) writing a first binary signal into said second memory locations of said control memory if a condition is satisfied which states that an incoming signal of a multi-channel call is located between the beginning of a first outgoing frame and the end of a first incoming frame which at least partially overlaps the first outgoing frame and a corresponding outgoing signal in said first outgoing frame, if shifted by an amount equal to said phase difference toward a second, subsequent outgoing frame will be located between the beginning of said second outgoing frame and the end of a second, subsequent incoming frame, or generating a second signal when said condition if not satisfied, (a 3 ) writing a second binary signal into said second memory locations of said control memory if said condition is not satisfied, and (b) reading signals from said first and second memory locations of said control memory in accordance with said read address of said control memory; exclusive-OR gate means for receiving said first and second binary signals from said control memory and a most significant bit of said read address of said control memory; and a multiplexer having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminal connected to said outgoing highway, said multiplexer alternately establishing a connection from one of said first and second input terminals to said outgoing highway in response to an output signal from said exclusive-OR gate means.

Claim 10

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are carried; an outgoing highway for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channels calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector connected to said incoming highway for detecting the beginning of said incoming frame; means for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a demultiplexer having an input terminal connected to said incoming highway and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer alternately establishing a connection from said incoming highway to one of said first and second output terminals in response to a most significant bit of said write address; a control memory having first and second memory locations corresponding to the time slots of each of said incoming and outgoing frames; means for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; latch means for latching said read address as an indication of a phase difference between said incoming and outgoing frames in response to an output signal from said frame detector; and control means responsive to said latched address and to a time slot interchanging relationship between said incoming and outgoing highways for (a 1 ) writing a read address of said first and second time switch memories into said first memory locations of said control memory, (a 2 ) writing a first binary signal into said second memory locations of said control memory if a condition is satisfied which states that an incoming signal of a multi-channel call is located between the beginning of a first outgoing frame and the end of a first incoming frame which at least partially overlaps the first outgoing frame and a corresponding outgoing signal in said first outgoing frame, if shifted by an amount equal to said phase difference toward a second, subsequent outgoing frame will be located between the beginning of said second outgoing frame and the end of a second, subsequent incoming frame, or generating a second signal when said condition if not satisfied, (a 3 ) writing a second binary signal into said second memory locations of said control memory if said condition is not satisfied, and (b) reading signals from said first and second memory locations of said control memory in accordance with said read address of said control memory; exclusive-OR gate means for receiving said first and second binary signals from said control memory and a most significant bit of said read address of said control memory; and a multiplexer having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminal connected to said outgoing highway, said multiplexer alternately establishing a connection from one of said first and second input terminals to said outgoing highway in response to an output signal from said exclusive-OR gate means.

Claim 11

A time division switching system as claimed in claim 5, wherein said control means reverses the values of said first and second binary signals when said phase difference is greater than one-frame interval but smaller than two-frame interval.

Claim 12

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are contained; an outgoing highway for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channel calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; phase detector means for detecting a phase difference between said incoming and outgoing frames; and control means for (a) writing signals on said incoming highway into an alternate one of said first and second time switch memories, (b) generating a first signal when the time slot of at least one signal of a given multi-channel call of a given incoming frame is later than the time slot of a corresponding signal on a corresponding outgoing frame, or a second signal when the time slots of all signals of said given multi-channel call on said given incoming frame are earlier than the time slots of respectively corresponding signals on said corresponding outgoing frame, and (c) reading all signals of said given multi-channel call from one of said first and second time switch memories into specified time slots of an outgoing frame subsequent to said corresponding outgoing frame in accordance with said phase difference and a switching signal in the presence of said first signal and reading all signals of said given multi-channel call from one of said time switch memories into said corresponding outgoing frame in accordance with said phase difference and said time slot interchanging relationship in the presence of said second signal.

Claim 13

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are contained; an outgoing highway for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channel calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; phase detector means for detecting a phase difference between said incoming and outgoing frames; and control means for (a) writing signals on said incoming highway into an alternate one of said first and second time switch memories, (b) generating a first signal when the time slot of at least one signal of a given multi-channel call of a given incoming frame is later than the time slot of a corresponding signal on a corresponding outgoing frame, or a second signal when the time slots of all signals of said given multi-channel call on said given incoming frame are earlier than the time slots of respectively corresponding signals on said corresponding outgoing frame, and (c) reading all signals of said given multi-channel call from one of said first and second time switch memories into specified time slots of an outgoing frame subsequent to said corresponding outgoing frame in accordance with said phase difference and a switching signal in the presence of said first signal and reading all signals of said given multi-channel call from one of said time switch memories into said corresponding outgoing frame in accordance with said phase difference and said time slot interchanging relationship in the presence of said second signal.

Claim 14

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are carried; an outgoing highway for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channel calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector connected to said incoming highway for detecting the beginning of said incoming frame; means for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a demultiplexer having an input terminal connected to said incoming highway and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer alternately establishing connection from said incoming highway to one of said first and second output terminals in the presence of a most significant bit of said write address; a control memory having first and second memory locations corresponding to the time slots of each of said incoming and outgoing frames; means for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; latch means for latching said read address as an indication of a phase difference between said incoming and outgoing frames in response to an output signal from said frame detector; and control means responsive to said latched address and to a time slot interchanging relationship between said incoming and outgoing highways for (a 1 ) writing a read address of said first and second time switch memories into said first memory locations of said control memory, (a 2 ) writing a first binary signal into said second memory locations of said control memory if the time slot of at least one signal of a given multi-channel call on a given incoming frame is later than the time slot of a corresponding signal of a corresponding outgoing frame, (a 3 ) writing a second binary signal into said second memory locations of said control memory when the time slots of all signals of said given multi-channel call on said given incoming frame are earlier than the time slots of respectively corresponding signals on said corresponding outgoing frame, and (b) reading signals from said first and second memory locations of said control memory in accordance with said read address of said control memory; exclusive-OR gate means for receiving said first and second binary signals from said control memory and a most significant bit of said read address of said control memory; and a multiplexer having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminals connected to said outgoing highway, said multiplexer alternately establishing a connection from one of said first and second input terminals to said outgoing highway in response to an output signal from said exclusive-OR gate means.

Claim 15

A time division switching system for multi-channel calls, comprising: an incoming highway for supporting a series of incoming frames having time slots in which signals of said multi-channel calls are carried; an outgoing highway for supporting a series of outgoing frames having time slots in which corresponding signals of said multi-channel calls are carried; first and second time switch memories each having memory locations corresponding to the time slots of each of said incoming and outgoing frames; a frame detector connected to said incoming highway for detecting the beginning of said incoming frame; means for supplying a write address to said first and second time switch memories in synchronism with the time slots of said incoming frame; a demultiplexer having an input terminal connected to said incoming highway and first and second output terminals connected respectively to input terminals of said first and second time switch memories, said demultiplexer alternately establishing connection from said incoming highway to one of said first and second output terminals in the presence of a most significant bit of said write address; a control memory having first and second memory locations corresponding to the time slots of each of said incoming and outgoing frames; means for generating a read address of said control memory in synchronism with the time slots of said outgoing frame; latch means for latching said read address as an indication of a phase difference between said incoming and outgoing frames in response to an output signal from said frame detector; and control means responsive to said latched address and to a time slot interchanging relationship between said incoming and outgoing highways for (a 1 ) writing a read address of said first and second time switch memories into said first memory locations of said control memory, (a 2 ) writing a first binary signal into said second memory locations of said control memory if the time slot of at least one signal of a given multi-channel call on a given incoming frame is later than the time slot of a corresponding signal of a corresponding outgoing frame, (a 3 ) writing a second binary signal into said second memory locations of said control memory when the time slots of all signals of said given multi-channel call on said given incoming frame are earlier than the time slots of respectively corresponding signals on said corresponding outgoing frame, and (b) reading signals from said first and second memory locations of said control memory in accordance with said read address of said control memory; exclusive-OR gate means for receiving said first and second binary signals from said control memory and a most significant bit of said read address of said control memory; and a multiplexer having first and second input terminals connected respectively to output terminals of said first and second time switch memories and an output terminals connected to said outgoing highway, said multiplexer alternately establishing a connection from one of said first and second input terminals to said outgoing highway in response to an output signal from said exclusive-OR gate means.

Claim 16

A time division switching system as claimed in claim 8, wherein said control means reverses the values of said first and second binary signals when said phase difference is greater than one-frame interval but smaller than two-frame interval.