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US5038351A
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Coded mark inversion block synchronization circuit
Assignee: Hitachi Ltd
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Filing: 1989-04-18
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Granted: 1991-08-06
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Expires: 2009-04-18
Abstract
Abstract A CMI block synchronization circuit includes a clock deriving circuit, CMI decoding circuit, signal selection determining circuit and a selection circuit. In the clock deriving circuit, a clock CLK o having the same phase as a binary signal and a clock CLK.sub.π having a phase which is different 180° from the clock CLK o are derived from an inputted CMI code signal. In the CMI decoding circuit, the inputted CMI code signal is decoded by using the clocks derived and violating bits are detected. In the signal selection determining circuit, the clocks CLK o and CLK.sub.π are counted respectively. Only when one of the count values is equal to or higher than a setting value and another count value is lower than another setting value is it regarded that a block asynchronization is caused in decoding the CMI code signal. In this case, the decoded output being selected until that time is changed over to another decoded output, whereby the block synchronization is retained even during burst errors.
Inventors
- 👤 Kazutaka Sakai
- 👤 Yoshihiro Ashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:04
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H03; H03M; H03M5/00; H03M5/02; H03M5/04; H03M5/14; H03M5/145; H04L7/02; H04L7/033; H04L7/0337
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
223 words
A CMI block synchronization circuit comprising: clock deriving means for deriving, from an inputted CMI code, a first clock having a period substantially identical to a bit period of a binary code from said inputted CMI code and a second clock having a phase difference of 180 degrees from said inputted CMI code; first decoding and detecting means for decoding said inputted CMI code on the basis of said first clock and detecting first violating bits from said inputted CMI code; second decoding and detecting means for decoding said inputted CMI code on the basis of said second clock and detecting second violating bits from said inputted CMI code; selection means for selecting one of decoded signals outputted from said first and second decoding and detecting means; means for individually counting said first and second violating bits from said first and second decoding and detecting means and comparing individual counts of said first and second violating bits with respective setting values; and signal selection determining means for causing said selection means to select one of said decoded signals, when one of said individual counts of said first and second violating bits is equal to or higher than its respective setting value and the other one of said individual counts of said first and second violating bits is lower than its respective setting value.
Claim 2
Dependent Claim
223 words
A CMI block synchronization circuit comprising: clock deriving means for deriving, from an inputted CMI code, a first clock having a period substantially identical to a bit period of a binary code from said inputted CMI code and a second clock having a phase difference of 180 degrees from said inputted CMI code; first decoding and detecting means for decoding said inputted CMI code on the basis of said first clock and detecting first violating bits from said inputted CMI code; second decoding and detecting means for decoding said inputted CMI code on the basis of said second clock and detecting second violating bits from said inputted CMI code; selection means for selecting one of decoded signals outputted from said first and second decoding and detecting means; means for individually counting said first and second violating bits from said first and second decoding and detecting means and comparing individual counts of said first and second violating bits with respective setting values; and signal selection determining means for causing said selection means to select one of said decoded signals, when one of said individual counts of said first and second violating bits is equal to or higher than its respective setting value and the other one of said individual counts of said first and second violating bits is lower than its respective setting value.
Claim 3
Dependent Claim
156 words
A CMI block synchronization method comprising the steps of: deriving, from an inputted CMI code, a first clock having a period substantially identical to a bit period of a binary code from a second clock having a phase difference of 180 degrees from said first clock; obtaining decoded signals by decoding said inputted CMI code on the basis of said first and second clocks; detecting and counting violating bits of said decoded signals in each of a plurality of supervisory sections; comparing counts of said violating bits with respective setting values; and selecting and outputting a decoded signal on the basis of said second clock, when a count of violating bits of said decoded signal on the basis of said first clock is equal to or larger than a setting value and a count of violating bits of the other decoded signal on the basis of said second clock is lower than the other setting value.
Claim 4
Dependent Claim
156 words
A CMI block synchronization method comprising the steps of: deriving, from an inputted CMI code, a first clock having a period substantially identical to a bit period of a binary code from a second clock having a phase difference of 180 degrees from said first clock; obtaining decoded signals by decoding said inputted CMI code on the basis of said first and second clocks; detecting and counting violating bits of said decoded signals in each of a plurality of supervisory sections; comparing counts of said violating bits with respective setting values; and selecting and outputting a decoded signal on the basis of said second clock, when a count of violating bits of said decoded signal on the basis of said first clock is equal to or larger than a setting value and a count of violating bits of the other decoded signal on the basis of said second clock is lower than the other setting value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-05 | 1995-02-04 | 1995-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-05 | 1999-02-04 | 1999-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-05 | 2003-02-04 | 2003-08-06 | $7700.00 | Window Closed / Lapsed |