Non-volatile memory cell with ferroelectric capacitor having logically inactive electrode

Claim 2

In a non-volatile memory array including a source of voltage and a bit line having a parasitic capacitive reactance, a ferroelectric memory cell comprising a capacitor having opposed electrode plates, means connecting the source to one of the electrode plates of the capacitor for applying a constant voltage thereto under two distinct hysteresis states, switching means interconnected between the other of the electrode plates of the capacitor and the bit line for transfer of charge to the bit line during read operations by discharge of the capacitor, means connected to the switching means for isolating the bit line from the capacitor between said read operations, sense means connected to the bit line for detecting changes in voltage level therein during said read operations and means for restoring the capacitor to one of two hysteresis states thereof in response to one of the detected changes in the voltage level.

Claim 3

The combination of claim 1 wherein said switching means is a transistor having a control electrode connected to the logic controlled means.

Claim 4

The combination of the claim 2 wherein said sense means includes means for amplifying said changes in the voltage level, and said restoring means includes logic gate means connected to the amplifying means for applying an amplified output thereof to the capacitor through the transistor upon completion of the read operations.

Claim 5

The combination of claim 1 wherein said sense means includes means for amplifying said changes in the voltage level, and said restoring means includes switch means connected to the amplifying means for applying an amplified output thereof to the capacitor through the switching means upon completion of the read operations.

Claim 6

The combination of claim 1 wherein said capacitor conducts current through an equivalent resistive shunt path smaller in resistance than that of the switching means in a non-conductive state to isolate the capacitor from the bit line between said read operations.

Claim 7

The combination of claim 5 wherein said parasitic capacitive reactance of the bit line is substantially higher than that of the capacitor.

Claim 8

In combination with a random access memory having a source of voltage, a bit line, a capacitor, means connected to the voltage source for applying and maintaining a fixed voltage on the capacitor and switching means operatively connected between the capacitor and the bit line for isolation of the capacitor from the bit line between writing and readout operations, said capacitor consisting of ferroelectric means for storing logic data therein dependent on two hysteresis states thereof, address means for selectively rendering the switching means operative only during said writing and readout operations to transfer non-zero charge to the bit line and sensing means connected to the bit line for detection of said transfer of the non-zero charge by the switching means.

Claim 9

In combination with a random access memory having a source of voltage, a bit line, a capacitor, means connected to the voltage source for applying and maintaining a fixed voltage on the capacitor and switching means operatively connected between the capacitor and the bit line for isolation of the capacitor from the bit line between writing and readout operations, said capacitor consisting of ferroelectric means for storing logic data therein dependent on two hysteresis states thereof, address means for selectively rendering the switching means operative only during said writing and readout operations to transfer non-zero charge to the bit line and sensing means connected to the bit line for detection of said transfer of the non-zero charge by the switching means.

Claim 10

In a non-volatile ferroelectric memory having a plurality of cells coupled in columns by bit lines and in rows by word lines, each of said cells comprising a capacitor having first and second plate electrodes, polarization of said capacitors corresponding to data stored therewithin; the improvement residing in a plate line distinct from said bit lines and said word lines coupled to the first of the plate electrodes of the capacitors, each of said cells further including switching means for coupling said second plate electrode of the capacitor to the corresponding one of the bit lines and means coupled to the switching means and delete "logically" for logically controlling the capacitor in each of the cells exclusively through the second plate electrodes thereof.

Claim 11

In a non-volatile ferroelectric memory having a plurality of cells coupled in columns by bit lines and in rows by word lines, each of said cells comprising a capacitor having first and second plate electrodes, polarization of said capacitors corresponding to data stored therewithin; the improvement residing in a plate line distinct from said bit lines and said word lines coupled to the first of the plate electrodes of the capacitors, each of said cells further including switching means for coupling said second plate electrode of the capacitor to the corresponding one of the bit lines and means coupled to the switching means and delete "logically" for logically controlling the capacitor in each of the cells exclusively through the second plate electrodes thereof.

Claim 12

The memory of claim 8 further comprising a sense amplifier coupled to each of said bit lines.

Claim 13

A non-volatile ferroelectric memory comprising an array of memory cells arranged in rows and columns, each of said rows corresponding to a respective word line, each said columns corresponding to a respective bit line, a sense amplifier coupled to each of said bit lines; each of said memory cells comprising a capacitor having a first plate electrode that is logically inactive and a second plate electrode and transistor means for coupling said second plate electrode to the corresponding one of said bit lines; a corresponding one of said word lines being coupled to the transistor means; and a plate line coupled to the first plate electrode of each of said capacitors in said array distinct from said word lines and said bit lines to maintain the same logically inactive.

Claim 14

A non-volatile ferroelectric memory comprising an array of memory cells arranged in rows and columns, each of said rows corresponding to a respective word line, each said columns corresponding to a respective bit line, a sense amplifier coupled to each of said bit lines; each of said memory cells comprising a capacitor having a first plate electrode that is logically inactive and a second plate electrode and transistor means for coupling said second plate electrode to the corresponding one of said bit lines; a corresponding one of said word lines being coupled to the transistor means; and a plate line coupled to the first plate electrode of each of said capacitors in said array distinct from said word lines and said bit lines to maintain the same logically inactive.

Claim 15

A non-volatile method of reading data from and restoring data to a memory cell selected from an array organized into rows and columns, each memory cell in the array including a ferroelectric capacitor having two plates and two polarization states established therebetween corresponding to two binary logic levels and a switchable device coupled to one of the plates of the capacitor, comprising the steps of: applying a non-zero voltage across the plates of said capacitors in said cells; applying a signal to a word line along the row corresponding to a selected memory cell for turning on the switchable device located therein thereby coupling said one of the plates of one of the capacitors to one of the bit lines corresponding to the column thereof; evaluating the signal developed on the bit line corresponding to the selected memory cell to determine the logic states of the capacitor; and limiting logical control of the polarization states exclusively through said one of the two plates of the capacitor.

Claim 16

A non-volatile method of reading data from and restoring data to a memory cell selected from an array organized into rows and columns, each memory cell in the array including a ferroelectric capacitor having two plates and two polarization states established therebetween corresponding to two binary logic levels and a switchable device coupled to one of the plates of the capacitor, comprising the steps of: applying a non-zero voltage across the plates of said capacitors in said cells; applying a signal to a word line along the row corresponding to a selected memory cell for turning on the switchable device located therein thereby coupling said one of the plates of one of the capacitors to one of the bit lines corresponding to the column thereof; evaluating the signal developed on the bit line corresponding to the selected memory cell to determine the logic states of the capacitor; and limiting logical control of the polarization states exclusively through said one of the two plates of the capacitor.

Claim 17

The method of claim 11 wherein said evaluating step includes operating a sense amplifier coupled to said bit line.

Claim 18

The method of claim 12 wherein said applied non-zero voltage is maintained constantly on the other of the plates of the capacitors.

Claim 19

The method of claim 11 wherein said applied non-zero voltage is maintained constant on the other of the plates of the capacitors.

Claim 20

In a non-volatile, self-restoring memory array comprising a plurality of cells selectively addressed through word lines to store binary logic data received during write operations and a plurality of bit lines to which voltage is applied during the write operations and through which the binary logic data is readout from the selectively addressed cells during read operations, a ferroelectric storage capacitor in each of the cells having opposed electrode plates and switching means operatively connected to a corresponding one of the word lines for electrically interconnecting one of the electrode plates to a corresponding one of the bit lines in response to selective address, the improvement residing in: means for maintaining a constant voltage on the other of the electrode plates of the capacitor in each of the cells during the write operations to effect said storing of the binary logic data in the storage capacitors thereof.

Claim 21

In a non-volatile, self-restoring memory array comprising a plurality of cells selectively addressed through word lines to store binary logic data received during write operations and a plurality of bit lines to which voltage is applied during the write operations and through which the binary logic data is readout from the selectively addressed cells during read operations, a ferroelectric storage capacitor in each of the cells having opposed electrode plates and switching means operatively connected to a corresponding one of the word lines for electrically interconnecting one of the electrode plates to a corresponding one of the bit lines in response to selective address, the improvement residing in: means for maintaining a constant voltage on the other of the electrode plates of the capacitor in each of the cells during the write operations to effect said storing of the binary logic data in the storage capacitors thereof.

Claim 22

A non-volatile method of reading data from and restoring said data to ferroelectric capacitors in memory cells of an array organized into rows and columns by word lines and bit lines, respectively, each of the memory cells including a switchable device connected to the capacitor thereof which has two polarization states corresponding to binary logic of the data thereby established between opposed electrode plates, the steps of: applying signals to the word lines along the rows for turning on the switchable devices of selected ones of the memory cells thereby coupling one of the plates of the capacitors to the bit lines corresponding to the columns; applying a fixed non-zero voltage across the plates of the capacitors in a plurality of said memory cells along the rows through said one of the plates while said switchable devices in said cells are turned on; detecting the voltage levels on the bit lines corresponding to the selected memory cells to determine the logic of the data; and terminating the word line signals in time spaced relation to said determination of the logic of the data.

Claim 23

A non-volatile method of reading data from and restoring said data to ferroelectric capacitors in memory cells of an array organized into rows and columns by word lines and bit lines, respectively, each of the memory cells including a switchable device connected to the capacitor thereof which has two polarization states corresponding to binary logic of the data thereby established between opposed electrode plates, the steps of: applying signals to the word lines along the rows for turning on the switchable devices of selected ones of the memory cells thereby coupling one of the plates of the capacitors to the bit lines corresponding to the columns; applying a fixed non-zero voltage across the plates of the capacitors in a plurality of said memory cells along the rows through said one of the plates while said switchable devices in said cells are turned on; detecting the voltage levels on the bit lines corresponding to the selected memory cells to determine the logic of the data; and terminating the word line signals in time spaced relation to said determination of the logic of the data.

Claim 24

The method of claim 16 including the step of: transferring voltage from the bit lines to the other plates through the turned on switchable devices in order to establish the polarization states corresponding to the binary logic of the data.

Claim 25

In a cell of a memory array having word lines and bit lines, a capacitor with opposed electrodes and a switching device interconnected between one of the electrodes and a corresponding one of the bit lines under control of address signals transmitted through a corresponding one of the word lines controlling transfer of voltages to and from the capacitor, the improvement residing in: ferroelectric means establishing a shunting resistance across the capacitor for enabling storage and readout of data with respect to the capacitor in response to said controlled transfer of voltage from and to the bit line under said control of the address signals and means for limiting said controlled transfer of voltage to said one of the electrodes of the capacitor.

Claim 26

In a cell of a memory array having word lines and bit lines, a capacitor with opposed electrodes and a switching device interconnected between one of the electrodes and a corresponding one of the bit lines under control of address signals transmitted through a corresponding one of the word lines controlling transfer of voltages to and from the capacitor, the improvement residing in: ferroelectric means establishing a shunting resistance across the capacitor for enabling storage and readout of data with respect to the capacitor in response to said controlled transfer of voltage from and to the bit line under said control of the address signals and means for limiting said controlled transfer of voltage to said one of the electrodes of the capacitor.

Claim 27

A non-volatile ferroelectric memory comprising an array of memory cells arranged in rows and columns, each of said rows corresponding to a respective word line, each of said columns corresponding to a respective bit line, a respective sense amplifier being coupled to each of said bit lines; each memory cell comprising a ferroelectric capacitor having first and second plate electrodes and a transistor located within said cell for coupling said first electrode of said ferroelectric capacitor to the corresponding bit line; said word line being coupled to a control electrode of said transistor; and a plate line distinct from the word and bit lines coupled to the second plate electrode of said ferroelectric capacitor, said plate line being coupled to second plate electrodes of a plurality of capacitors in said array, and a source of constant voltage coupled to said plate line.

Claim 28

A non-volatile ferroelectric memory comprising an array of memory cells arranged in rows and columns, each of said rows corresponding to a respective word line, each of said columns corresponding to a respective bit line, a respective sense amplifier being coupled to each of said bit lines; each memory cell comprising a ferroelectric capacitor having first and second plate electrodes and a transistor located within said cell for coupling said first electrode of said ferroelectric capacitor to the corresponding bit line; said word line being coupled to a control electrode of said transistor; and a plate line distinct from the word and bit lines coupled to the second plate electrode of said ferroelectric capacitor, said plate line being coupled to second plate electrodes of a plurality of capacitors in said array, and a source of constant voltage coupled to said plate line.

Claim 29

In a non-volatile electronic memory system having a source of constant voltage, a ferroelectric memory cell and means connected to the cell for retrieval and transfer of information, said ferroelectric cell including an electrically polarizable capacitor directly connected to the source of voltage, a data line and transistor switch means connected to the data line and the capacitor for controlling said retrieval and transfer of the information with respect to the data line.

Claim 30

In a non-volatile electronic memory system having a source of constant voltage, a ferroelectric memory cell and means connected to the cell for retrieval and transfer of information, said ferroelectric cell including an electrically polarizable capacitor directly connected to the source of voltage, a data line and transistor switch means connected to the data line and the capacitor for controlling said retrieval and transfer of the information with respect to the data line.