Number conversion apparatus

Claim 1

A number conversion circuit for converting an N-bit input number in a form of an integer, a floating-point, or a FRACT number into an M-bit number in Modulo 256 format with multiple tap points, where M>N, said Modulo 256 format comprising an exponent having at least one exponent bit, and an N-bit mantissa having at least one signed integer bit and at least one fraction bit, said exponent being such that each increase by a value of 1 of said exponent is equivalent to multiplying said mantissa by 256, said number conversion circuit comprising: integer and FRACT number converting means for converting an integer or a FRACT input number into an equivalent Modulo 256 number format, said FRACT number comprising an integer and a fractional portions, said integer and FRACT number converting means comprising; aligning means for aligning a least significant bit (LSB) of said input number at a rightmost bit space of said M-bit number in Modulo 256 format; first shift register for generating a normalized mantissa of said Modulo 256 format by shifting said input number leftward in 8-bit steps; and first exponent calculating means for subtracting a first exponent value in said exponent by 1 for each said 8-bit step, said exponent value being equivalent to shifting a binary point of said integer or FRACT number to be aligned with a binary point of said Modulo 256 format, wherein said first exponent value is a first predetermined value for integer number conversion and a second predetermined value for FRACT number conversion; floating-point number converting means for converting a floating-point number into an equivalent Modulo 256 format number, said floating-point number comprising a sign bit, an exponent number ("E") representing 2's power and an unsigned mantissa, said floating-point number converting means comprising; aligning means for aligning a LSB of said integer input number at a rightmost bit space of said M-bit number in Modulo 256 format; sign-converting means for converting said unsigned mantissa of said floating-point number into a signed mantissa of said Modulo 256 format; second shift register for generating a normalized mantissa of said Modulo 256 format by shifting said signed mantissa leftward R bits, if E>=8 and R=E-8×F, F being an integer, or shifting said signed mantissa leftward E bits if E<8; and second exponent calculating means for setting said exponent of said Modulo 256 to (F+8) if E>=8, or setting said exponent of said Modulo 256 format to 8 if E<8; control means for selecting a valid output number in said Modulo 256 format from said integer and FRACT number converting means if an integer number or FRACT number is converted into Modulo 256 format, and floating-point number converting means if a floating-point number is converted into Modulo 256 format; whereby an output number in said Modulo 256 format is generated.