US4016560A
Expired / Lapsed
US
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Fractional binary to decimal converter
Assignee: United States Department of the Navy
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Filing: 1976-03-09
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Granted: 1977-04-05
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Expires: 1996-03-09
Abstract
Abstract The present invention relates to a simplified apparatus for converting a ary fraction input into a Natural Binary Coded Decimal (8421 code) and subsequently into a decimal output with the proper sign. The invention provides means for selectively shifting and summing the binary fraction to effect a multiplication by ten. An integer portion to the left of a fixed binal point and a remaining fraction portion to the right are produced. The integer portion is extracted as a BCD character which is converted via a nixie display into decimal form. Shifting and summing successive remaining fractions and displaying successive integer portions produces a final decimal number which corresponds to the binary fraction input.
Inventors
- 👤 Robert W. Fowler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:58
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/02; H03M7/12
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
253 words
An apparatus for converting an n-bit binary fraction word into a word in decimal form comprising: a read-in line on which the n bits of a binary fraction word are carried, means for generating a word pulse during the n bits of alternating word-times, means connected to the word pulse generator for shifting the word pulse two bits in the direction of higher significance, thereby generating a shifted pulse, a first stage having the binary fraction word on the read-in line as an input, a series of successive stages, connected to and in seriatim following the first stage, each successive stage having as an input a remaining binary fraction generated by its preceding stage, wherein the first stage and each successive stage comprises: means for ANDING the input of each stage with the generated word pulse from the word-pulse generating means thereby producing a first gate input, means for shifting the input two bits in the direction of higher significance, thereby generating a shifted input, means for ANDing the shifted input of each stage with the shifted word pulse, thereby producing a second gate-input, means for summing the first gate-input and the second gate-input thereby producing a summed output, means for shifting the summed output two bits in the direction of higher significance, thereby generating the input for the next successive stage, and means for grouping together the four most significant bits of each generated input as a binary-coded decimal, and means for ordering the binary-coded decimals in decreasing significance for successive stages.
Claim 2
Independent Claim
253 words
An apparatus for converting an n-bit binary fraction word into a word in decimal form comprising: a read-in line on which the n bits of a binary fraction word are carried, means for generating a word pulse during the n bits of alternating word-times, means connected to the word pulse generator for shifting the word pulse two bits in the direction of higher significance, thereby generating a shifted pulse, a first stage having the binary fraction word on the read-in line as an input, a series of successive stages, connected to and in seriatim following the first stage, each successive stage having as an input a remaining binary fraction generated by its preceding stage, wherein the first stage and each successive stage comprises: means for ANDING the input of each stage with the generated word pulse from the word-pulse generating means thereby producing a first gate input, means for shifting the input two bits in the direction of higher significance, thereby generating a shifted input, means for ANDing the shifted input of each stage with the shifted word pulse, thereby producing a second gate-input, means for summing the first gate-input and the second gate-input thereby producing a summed output, means for shifting the summed output two bits in the direction of higher significance, thereby generating the input for the next successive stage, and means for grouping together the four most significant bits of each generated input as a binary-coded decimal, and means for ordering the binary-coded decimals in decreasing significance for successive stages.
Claim 3
Dependent Claim
36 words
An apparatus as defined in claim 1, further comprising: a read pulse generator for generating a pulse which controls the time at which a binary fraction word carried on the read-in line is to be converted.
Claim 4
Dependent Claim
28 words
An apparatus as defined in claim 2 wherein said read pulse generator comprises: manual mode circuitry, automatic adjustable mode circuitry, and means for selectively switching to either mode.
Claim 5
Dependent Claim
47 words
An apparatus as defined in claim 3, wherein the automatic adjustable mode circuitry comprises: a ring counter for determining a base time interval and an R adder connected to the ring counter for determining how many base time intervals must pass before a read pulse is generated.
Claim 6
Dependent Claim
93 words
An apparatus as defined in claim 1 further comprising: sign determination logic circuitry, having the binary fraction word on the read-in line as an input, for determining the sign of the binary fraction word, means, receiving the output of the sign determination logic circuitry, for complementing negative binary fraction words and for selectively passing through positive and complemented negative binary traction words to the first stage, and sign bit output indicator means connected to the output of the sign bit determination logic circuitry for indicating the sign of the converted decimal form word.
Claim 7
Dependent Claim
51 words
An apparatus as defined in claim 5 wherein the sign determination logic circuitry comprises negative logic circuitry and the complementing and pass through means comprises positive TTL circuitry and wherein a translator is interposed between the logic circuitry and the TTL circuitry for making the logic circuitry and TTL circuitry compatible.
Claim 8
Dependent Claim
33 words
An apparatus as defined in claim 5, further comprising: a display which receives the binary-coded decimals from the ordering means for indicating in decimal form the binary-coded decimals generated in the successive stages.
Claim 9
Dependent Claim
58 words
An apparatus as defined in claim 5, where n equals 25, further comprising: a 25 bit register for storing bits read in from the read-in line and gate circuitry means for connecting the 25 bit register to the word pulse generator, such that the 25 bits in the register are converted only when a word pulse is generated.
Claim 10
Dependent Claim
38 words
An apparatus as defined in claim 8 which includes nine successive stages, further comprisng: 10 decimal display indicators, connected to the binary-coded decimal ordering means, for displaying the binary-coded decimals generated by the stages in 10-digit decimal form.
Claim 11
Dependent Claim
88 words
An apparatus as defined in claim 8, wherein the means for grouping together the 4 most significant bits of each generated input comprises: a shift register, having the generated input as an input, for producing four outputs equivalent to the generated input shifted 0, 1, 2, and 3 bits, respectively, in the direction of higher significance, and means, connected to the shift register, for reading off the binary value of the 0-, 1-, 2- and 3-bit shifted outputs at the fourth least significant bit-time of the previous word-time.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-04-04 | 1980-10-04 | 1981-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-04-04 | 1984-10-04 | 1985-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-04-04 | 1988-10-04 | 1989-04-05 | $7700.00 | Window Closed / Lapsed |