Data processing system having dual arbiter for controlling access to a system bus

Claim 1

A data processing system comprising at least a first and a second processor connected to a system bus for access to common resources, a timing unit connected to said first and second processors, said timing unit generating two periodic timing signals having equal frequency, but out of phase the one as to the other, each period of said periodic timing signals comprising two phases, a phase at least of each one of said periodic timing signals being time distinct and non overlapped to the corresponding phase of the other of said periodic timing signals, and arbitration logic means connected to said timing unit and to said first and second processors for controlling access to said system bus by said first and second processors, said first processor being clocked by one of said periodic timing signals for asserting a first request signal requesting access to said system bus in said time distinct phase of said one periodic timing signal and for providing said first request signal to said arbitration logic means, said second processor being clocked by the other of said periodic timing signals for asserting a second request signal requesting access to said system bus in said time distinct phase of said other periodic timing signal, and said arbitration logic means receiving said two periodic timing signals and said first and second request signals asserted during each of said time distinct and non overlapped phases of said periodic signals, and asserting a first enable signal granting bus access to said first processor if said first request signal is asserted and said second request signal is deasserted, and asserting a second enable signal granting bus access to said second processor if said second request signal and said first request signal is deasserted.