Construction process for a self-aligned transistor

Claim 2

Process of constructing a self-aligned transistor, which is supported by a substrate and includes several layers of semiconducting material, and gate, source and drain metallisations, comprising the steps of: depositing a layer of resin on the semiconducting material, masking by optical means to isolate at least one pattern, at the site of the gate, the pattern being of dimensions which are at the limit of the resolution power of said optical means, etching the sides of the pattern and the sides of the resin mask by plasma or ion etching, in the presence of O + ions, to give said sides a sloping profile, depositing a layer of silica on the mask and the pattern, masking the silica by a resin, between the pattern and the resin mask, and partial etching of the silica, then dry etching the two resin masks, leaving only two silica masks whose sloping sides leave between them an aperture of submicronic dimensions, through which is deposited the gate metallisation of the transistor.

Claim 3

Process of constructing a self-aligned transistor, according to claim 1, from a substrate of semi-insulating material, further comprising the steps of: a) depositing on the substrate a layer of silicon nitride, masking first with resin and then with silica, dissolving the resin and implanting silicon to create a trench of type N, and dissolving the silica mask, b) depositing and masking by a second resin mask, creating a resin pattern of dimensions corresponding to the resolution power of the optical means of masking used, and implanting silicon to create two N + trenches on the N trench, c) etching the sides of the pattern and the sides of the second mask by oxygen plasma or oxygen ion etching, to shrink the resin pattern and incline the sides, d) depositing a layer of silica on the second mask, on the resin pattern and in the gaps which separate the pattern from the second mask, and depositing a third resin mask on the layer of silica, e) dry oxygen etching the third resin mask, leaving only the resin in the gaps between the pattern and the second mask, then dry etching by CH F 3 +C 3 F 8 of the layer of silica, leaving only the two parts between the second and third resin masks, f) dry oxygen etching the resin masks and pattern, leaving two masks of silica whose sloping edges leave between them an aperture of dimensions smaller than the resolution power of said optical means, g) depositing a fourth resin mask, etching the silicon nitride layer at the side of the source and drain contacts, depositing the ohmic source and drain metallisations, and dissolving the fourth resin mask, h) depositing a fifth resin mask, dry etching by CH F 3 +C 3 F 8 of the silicon nitride layer at the site of the gate contact, through the aperture between the two silica masks, depositing of the Schottky gate metallisation, and dissolving the fifth resin mask, i) dissolving the two silica masks in a solution of HF+NH 4 F+H 2 O.

Claim 4

Process of constructing a self-aligned transistor, according to claim 1, from a substrate comprising layers of type N and N + formed by epitaxy, further comprising the steps of: a) depositing and masking by a first resin mask creating a resin pattern of dimensions corresponding to the power of resolution of said optical means, b) etching the sides of the pattern and the sides of the first mask by oxygen plasma or oxygen ion etching, to shrink the resin pattern and incline the sides, c) depositing a layer of silica on the first mask, on the resin pattern and in the gaps which separate the pattern from the second mask, and depositing a second resin mask on the layer of silica, d) dry oxygen etching of the second resin mask, leaving only the resin in the gaps between the pattern and the first mask, then dry etching by CH F 3 +C 3 F 8 of the layer of silica, leaving only the two parts between the first and second resin masks, e) dry oxygen etching the resin masks and pattern, leaving two masks of silica whose sloping edges leave between them an aperture of dimensions smaller than the resolution power of said optical means, f) depositing a third resin mask, depositing the ohmic source and drain metallisations, and dissolving the third resin mask, g) depositing a fourth resin mask, dry etching by CH F 3 +C 3 F 8 of the layer of N + semiconducting material at the site of the gate contact, through the aperture between the two silica masks, deposit of the Schottky gate metallisation, and dissolving the fourth resin mask, h) dissolving the two silica masks in a solution of HF+NH 4 F+H 2 O.

Claim 5

Process of constructing a self-aligned transistor, according to claim 1, wherein the silica masks have sloping sides which are rounded at their free end, this rounding contributing to the diminution of the aperture through which the gate is self-aligned.

Claim 6

Process of construction of a self-aligned transistor, according to claim 1, wherein the length of the aperture is adjusted by plasma etching or oxygen dry etching of the resin pattern of the second mask.