US5036370A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Thin film semiconductor array device
Assignee: Sharp Corp
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Filing: 1990-07-02
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Granted: 1991-07-30
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Expires: 2010-07-02
Abstract
Abstract The production of a thin film transistor array device having a gate wiring on an insulated substrate. The gate wiring has an inner gate wiring having a first metal layer formed on the insulated substrate and a second metal layer whose etching speed is faster than that of the first metal layer, the first metal layer and the second metal layer being overlapped so as to constitute a dual structure, and an outer gate wiring covering the inner gate wiring.
Inventors
- 👤 Makoto Miyago
- 👤 Hiroshi Oka
- 👤 Akihiko Imaya
- 👤 Hiroaki Kato
- 👤 Takayoshi Nagayasu
- 👤 Toshihiko Hirobe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:40
CPC Classifications
H; H01; H01S; H01S5/00; H01S5/40; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/136286; H01S5/02; H01S5/026; H01S5/0261; H01S5/04; H01S5/042; H01S5/0425; H01S5/04252; H01S5/04253; H01S5/04256; H10; H10D; H10D86/00; G02F1/136259; G02F1/136263; G02F1/13629; H01S5/0206
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
77 words
A thin film transistor array device having a gate wiring on an insulating substrate, the gate wiring comprising an inner gate wiring having a first metal layer formed on the insulating substrate and a second metal layer whose etching speed is faster than that of the first metal layer, the first metal layer and the second metal layer being overlapped so as to constitute a dual structure, and an outer gate wiring covering the inner gate wiring.
Claim 2
Dependent Claim
77 words
A thin film transistor array device having a gate wiring on an insulating substrate, the gate wiring comprising an inner gate wiring having a first metal layer formed on the insulating substrate and a second metal layer whose etching speed is faster than that of the first metal layer, the first metal layer and the second metal layer being overlapped so as to constitute a dual structure, and an outer gate wiring covering the inner gate wiring.
Claim 3
Dependent Claim
27 words
A thin film transistor array device according to claim 1, wherein the inner gate wiring has a smaller specific resistance than that of the outer gate wiring.
Claim 4
Dependent Claim
23 words
A thin film transistor array device according to claim 1 or 2, wherein the outer gate wiring is covered with an anodized film.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-29 | 1995-01-28 | 1995-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-29 | 1999-01-28 | 1999-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-29 | 2003-01-28 | 2003-07-30 | $7700.00 | Window Closed / Lapsed |