Patent US5036322A successfully refreshed from Google Patents.
US5036322A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital-to-analog converters with improved linearity
Assignee: Analog Devices Inc
•
Filing: 1989-06-02
•
Granted: 1991-07-30
•
Expires: 2009-06-02
Abstract
Abstract High accuracy is achieved by employing, in conventional DAC architectures, very accurate current sources. To create these high-accuracy current sources, the outputs of several smaller, less accurate, nominally equal current sources are summed. A procedure is taught for selecting the number of current sources to achieve an arbitrary degree of accuracy with a desired level of confidence. Assuming the current sources are taken from a population whose output currents deviate from a design value according to a normal distribution, the minimum number of constituent current sources, n, required to provide an accurate total current is given by the formula n=(Zσ/E) 2 , where Z is a number which corresponds to the probability that the output will fall within an error band E (i.e., a predetermined accuracy level) with a predetermined level of confidence, σ is the standard deviation of the population.
Inventors
- 👤 Jeffrey Barrow
- 👤 William J. Pratt
- 👤 Henry T. Tsuei
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 09:34
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/0617; H03M1/0634; H03M1/0643; H03M1/12; H03M1/34; H03M1/36; H03M1/361; H03M1/362; H03M1/365; H03M1/66; H03M1/68; H03M1/687; H03M1/74; H03M1/742; H03M1/745; H03M1/747; H03M1/78; H03M1/785
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
165 words
For use in an analog-to-digital converter, an assembly comprising: (a) an n-bit flash converter having (i) 2 n -1 comparators, each comparator having inverted and non-inverted outputs, and (ii) encoding means for providing from the comparator outputs an n-bit binary word corresponding to the set of comparator outputs; and (b) a digital-to-analog converter (DAC connected to the flash converter and having (i) 2 n -1 electronic switches, each operable in response to the state of the outputs of an associated one of said comparators for connecting a current, supplied to said switch, to a current summing node at which an analog output current is to be provided, and (ii) means for generating said currents the means for generating said currents comprising, for at lest one of said switches, a plurality of current sources whose outputs are summed together, the number of current sources in said plurality being sufficient to provide a desired current to within a predefined tolerance, and with a predetermined level of confidence.
Claim 2
Dependent Claim
165 words
For use in an analog-to-digital converter, an assembly comprising: (a) an n-bit flash converter having (i) 2 n -1 comparators, each comparator having inverted and non-inverted outputs, and (ii) encoding means for providing from the comparator outputs an n-bit binary word corresponding to the set of comparator outputs; and (b) a digital-to-analog converter (DAC connected to the flash converter and having (i) 2 n -1 electronic switches, each operable in response to the state of the outputs of an associated one of said comparators for connecting a current, supplied to said switch, to a current summing node at which an analog output current is to be provided, and (ii) means for generating said currents the means for generating said currents comprising, for at lest one of said switches, a plurality of current sources whose outputs are summed together, the number of current sources in said plurality being sufficient to provide a desired current to within a predefined tolerance, and with a predetermined level of confidence.
Claim 3
Dependent Claim
67 words
The apparatus of claim 1 wherein the number of current sources is at least equal to (Zσ/E) 2 , where σ is the standard deviation for the population of current sources from which the sample of current sources is taken, E is the error band or tolerance which is sought, and Z is a number representing the probability that the total current will be within said tolerance.
Claim 4
Dependent Claim
106 words
A digital-to-analog converter comprising: (a) a plurality of electronic switches, each operable in response to the state of a digital control signal applied thereto, for selectively connecting a current, supplied to said switch, to a current summing node at which an analog output current is to be provided; and (b) means for generating said currents, the means for generating said currents comprising, for at least one of said switches, a plurality of current sources whose outputs are summed together, the number of current sources is said plurality being sufficient to provide a desired current to within a predefined tolerance, and with the predetermined level of confidence.
Claim 5
Dependent Claim
106 words
A digital-to-analog converter comprising: (a) a plurality of electronic switches, each operable in response to the state of a digital control signal applied thereto, for selectively connecting a current, supplied to said switch, to a current summing node at which an analog output current is to be provided; and (b) means for generating said currents, the means for generating said currents comprising, for at least one of said switches, a plurality of current sources whose outputs are summed together, the number of current sources is said plurality being sufficient to provide a desired current to within a predefined tolerance, and with the predetermined level of confidence.
Claim 6
Dependent Claim
67 words
The apparatus of claim 1 wherein the number of current sources is at least equal to (Zσ/E) 2 , where σ is the standard deviation for the population of current sources from which the sample of current sources is taken, E is the error band or tolerance which is south, and Z is a number representing the probability that the total current will be within said tolerance.
Claim 7
Dependent Claim
257 words
A digital-to-analog converter comprising: (a) decoder means for deciding N most significant bits of an N+M bit digital work; (b) delay means for receiving and delaying the M least significant bits of the digital word; (c) a set of transparent latches for receiving the outputs of the decoder means and the delay means and for supplying at least two sets of outputs responsive to the state of the latch control signal applied thereto; (d) a first digital-to-analog converter (DAC) connected to receive from the transparent latches a first set of outputs comprising a plurality of the most significant bits; (e) a second DAC for receiving from the transparent latches a second set of outputs comprising a plurality of less significant bits; (f) each of said DAC's supplying at least one output current, which output currents are summed to produce the analog output current of the digital-to-analog converter; and (g) the first digital-to-analog converter comprising (1) a plurality of electronic switches, each operable in response to the state of a digital control signal applied thereto, for selectively connecting a current, supplied to said switch, to a current summing node at which an analog output current is to be provided, and (2) means for generating said currents, the means for generating said currents comprising, for at least one of said switches, a plurality of current sources whose outputs are summed together, the number of current said sources in said plurality being sufficient to provide a desired current to within a predefined tolerance, and with the predetermined level of confidence.
Claim 8
Dependent Claim
257 words
A digital-to-analog converter comprising: (a) decoder means for deciding N most significant bits of an N+M bit digital work; (b) delay means for receiving and delaying the M least significant bits of the digital word; (c) a set of transparent latches for receiving the outputs of the decoder means and the delay means and for supplying at least two sets of outputs responsive to the state of the latch control signal applied thereto; (d) a first digital-to-analog converter (DAC) connected to receive from the transparent latches a first set of outputs comprising a plurality of the most significant bits; (e) a second DAC for receiving from the transparent latches a second set of outputs comprising a plurality of less significant bits; (f) each of said DAC's supplying at least one output current, which output currents are summed to produce the analog output current of the digital-to-analog converter; and (g) the first digital-to-analog converter comprising (1) a plurality of electronic switches, each operable in response to the state of a digital control signal applied thereto, for selectively connecting a current, supplied to said switch, to a current summing node at which an analog output current is to be provided, and (2) means for generating said currents, the means for generating said currents comprising, for at least one of said switches, a plurality of current sources whose outputs are summed together, the number of current said sources in said plurality being sufficient to provide a desired current to within a predefined tolerance, and with the predetermined level of confidence.
Claim 9
Dependent Claim
67 words
The apparatus of claim 5 wherein the number of current sources is at least equal to (Zσ/E) 2 , where σ is the standard deviation for the population of current sources from which the sample of current sources is taken, E is the error band or tolerance which is sought, and Z is a number representing the probability that the total current will be within said tolerance.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-29 | 1995-01-28 | 1995-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-29 | 1999-01-28 | 1999-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-29 | 2003-01-28 | 2003-07-30 | $7700.00 | Window Closed / Lapsed |