Precise, high speed CMOS track (sample)/hold circuits

Claim 2

Circuitry comprising: first and second power terminals for the application therebetween of an operating potential; storage means coupled to a circuitry output terminal for storing information appearing at the circuitry output terminal for a useful period of time; a circuit leg comprising first, second, third and fourth diodes configured as a Wheatstone bridge with the cathode of the first diode and the anode of the second diode being coupled to a circuitry input terminal and with the circuitry output terminal being coupled to the cathode of the third diode and to the anode of the fourth diode; the anodes of the first and third diodes being coupled together at a first node; the cathodes of the third and fourth diodes being coupled together at a second node; and control means coupled to the circuit leg for controlling current flow through the diodes such that selectively current can be diverted away from the diodes, said control means comprising first, second, third and fourth transistors, each transistor having first and second electrodes defining the ends of a conduction path, and a control electrode for controlling the conductivity of the transistor; means coupling the conduction paths of said first and second transistors in series between said first node and said first power terminal; and means coupling the conduction paths of said third and fourth transistors in series between said second node and said second power terminal.

Claim 3

Circuitry comprising: first and second circuit legs; a current source coupled to the first and second circuit storage means coupled to a circuitry output terminal for storing information appearing at the output terminal for a useful period of time; the first circuit leg comprises first, second, third and fourth diodes configured as a Wheatstone bridge with the cathode of the first diode and the anode of the second diode being coupled to a circuitry input terminal and with the circuitry output terminal being coupled to the cathode of the third diode and to the anode of the fourth diode; the anodes of the first and third diodes being coupled together at a first node; the cathodes of the third and fourth diodes being coupled together at a second node; control means for controlling current flow through the first and second circuit legs such that current can essentially flow through one circuit leg or the other circuit leg; and wherein said second circuit leg comprises a first MOS transistor having first and second output terminals and a gate terminal; and wherein the control means comprises means for selectively reverse biasing the diodes and for selectively biasing on the first MOS transistor and for selectively biasing off the first MOS transistor; and wherein the means for reverse biasing the diodes comprises second and third MOS transistors each having first and second output terminals and a gate terminal with the first output terminal of the second transistor being coupled to the anodes of the first and third diodes and with the first output terminal of the second MOS transistor being coupled to the cathodes of the second and fourth diodes.

Claim 4

Circuitry comprising: first and second circuit legs; a current source coupled to the first and second circuit storage means coupled to a circuitry output terminal for storing information appearing at the output terminal for a useful period of time; the first circuit leg comprises first, second, third and fourth diodes configured as a Wheatstone bridge with the cathode of the first diode and the anode of the second diode being coupled to a circuitry input terminal and with the circuitry output terminal being coupled to the cathode of the third diode and to the anode of the fourth diode; the anodes of the first and third diodes being coupled together at a first node; the cathodes of the third and fourth diodes being coupled together at a second node; control means for controlling current flow through the first and second circuit legs such that current can essentially flow through one circuit leg or the other circuit leg; and wherein said second circuit leg comprises a first MOS transistor having first and second output terminals and a gate terminal; and wherein the control means comprises means for selectively reverse biasing the diodes and for selectively biasing on the first MOS transistor and for selectively biasing off the first MOS transistor; and wherein the means for reverse biasing the diodes comprises second and third MOS transistors each having first and second output terminals and a gate terminal with the first output terminal of the second transistor being coupled to the anodes of the first and third diodes and with the first output terminal of the second MOS transistor being coupled to the cathodes of the second and fourth diodes.

Claim 5

The circuitry of claim 2 wherein the diodes are Schottky barrier diodes.

Claim 6

The circuit of claim 3 wherein the storage means is a capacitor.

Claim 7

The circuitry of claim 2 wherein: the first circuit leg further comprises fourth and fifth MOS transistors each having a gate terminal and first and second output terminals; the first output terminal of the fourth transistor being coupled the anodes of the first and third diodes, and the first output terminal of the fifth transistor being coupled to the cathodes of the second and fourth diodes; and the second output terminal of the fourth transistor being coupled to a first portion of the current source, and the second output terminal of the fifth transistor being coupled to a second portion of the current source.

Claim 8

The circuitry of claim 5 wherein the first circuit leg further comprises a fifth diode whose anode is coupled to the first portion of the current source and whose cathode is coupled to the second output terminal of the fourth transistor, and a sixth diode whose anode is coupled to the second output terminal of the fifth transistor and whose cathode is coupled to the second portion of the current source.

Claim 9

The circuitry of claim 6 wherein: the current source comprises sixth and seventh MOS transistors each having first and second output terminals and a gate terminal; the first output terminal of the sixth transistor being coupled to the anode of the fifth diode; and the first output terminal of the seventh transistor being coupled to the cathode of the sixth diode.

Claim 10

The circuitry of claim 7 wherein the fourth and sixth transistors are of the same conductivity type and the fifth and seventh transistors are of the same conductivity type.

Claim 11

The circuitry of claim 8 wherein: the current source is an essentially constant current source and further comprises eighth, ninth, tenth and eleventh MOS transistors each having first and second output terminals and a gate terminal, and seventh and eighth diodes; the first output terminals of the sixth and eighth transistors being coupled together; the second output terminal and the gate terminal of the eighth transistor being coupled to the gate terminal of the sixth transistor and to an anode of the seventh diode; a cathode of the seventh diode being coupled to the first output terminal of the ninth transistor; the gate terminal and the second output terminal of the ninth transistor being coupled to gate terminals of the fourth, fifth and tenth transistors and to the first output terminal of the tenth transistor; the eighth and ninth transistors being of the same conductivity type as the fourth and sixth transistors; the second output terminal of the tenth transistor being coupled to an anode of the eighth diode, to the gate terminals of the seventh and eleventh transistors and to the first output terminal of the eleventh transistor; the second output terminals of the seventh and eleventh transistors being coupled together; and the tenth and eleventh transistors being of the same conductivity type as the fifth and seventh transistors.

Claim 12

The circuitry of claim 9 wherein: the fifth, sixth, seventh and eighth diodes are Schottky barrier diodes; and the fourth, sixth, eighth and ninth transistors are of one conductivity type and the fifth, seventh, tenth and eleventh transistors are of the opposite conductivity type.

Claim 13

The circuitry of claim 10 wherein the first, second and third transistors are of the same conductivity type.

Claim 14

The circuitry of claim 14 wherein the first transistor is of n-type conductivity and the fourth transistor is of p-type conductivity.

Claim 15

The circuitry of claim 10 wherein the first, third and fifth transistors are of n-type conductivity and the second and fourth transistors are of p-type conductivity.

Claim 16

Circuitry comprising: first and second circuit legs; a current source coupled to the first and second circuit legs; the first circuit leg comprises first, second, third and fourth diodes configured as a Wheatstone bridge and capacitive means with a circuitry input terminal coupled to the cathode of the first diode and to the anode of the second diode and with a circuitry output terminal coupled to the cathode of the third diode, to the anode of the fourth diode and to a first terminal of the capacitive means; the anodes of the first and third diodes being coupled together; the cathodes of the third and fourth diodes being coupled together; first means comprising MOS transistors coupled to the diodes for selectively reverse biasing the diodes to cut off current flow therethrough; and second means coupled to the second leg for selectively controlling current flow there through; the first and second means being adapted such that current can essentially only flow through one circuit leg or the other circuit leg.

Claim 17

Circuitry comprising: first and second circuit legs; a current source coupled to the first and second circuit legs; the first circuit leg comprises first, second, third and fourth diodes configured as a Wheatstone bridge and capacitive means with a circuitry input terminal coupled to the cathode of the first diode and to the anode of the second diode and with a circuitry output terminal coupled to the cathode of the third diode, to the anode of the fourth diode and to a first terminal of the capacitive means; the anodes of the first and third diodes being coupled together; the cathodes of the third and fourth diodes being coupled together; first means comprising MOS transistors coupled to the diodes for selectively reverse biasing the diodes to cut off current flow therethrough; and second means coupled to the second leg for selectively controlling current flow there through; the first and second means being adapted such that current can essentially only flow through one circuit leg or the other circuit leg.

Claim 18

The circuitry of claim 13 wherein the diodes are Schottky barrier diodes.

Claim 19

The circuit of claim 15 wherein the capacitive means is at least one capacitor.

Claim 20

The circuit of claim 16 wherein the current source is an essentially constant current source which is comprised of MOS transistors.

Claim 21

The circuit of claim 17 wherein the constant current means further comprises Schottky barrier diodes.

Claim 22

The circuit of claim 18 wherein the current source further comprises a voltage biasing circuit which is comprised of MOS transistors.

Claim 23

The circuit of claim 19 wherein the voltage biasing circuit further comprises a resistor.

Claim 24

A track/hold circuit comprising: first and second circuit legs; an essentially constant current source coupled to the first and second circuit legs; the first circuit leg comprises first, second, third and fourth diodes configured as a Wheatstone bridge; a track/hold circuit input terminal being coupled to the cathode of the first diode and to the anode of the second diode; a track/hold circuit output terminal being coupled to the cathode of the third diode, to the anode of the fourth diode and to a first terminal of a capacitor; the anodes of the first and third diodes being coupled together at a first node and said first node being coupled via the conduction path of a first transistor to a first portion of the current source; the cathodes of the third and fourth diodes being coupled together at a second node and said second node being coupled via the conduction path of a second transistor to a second portion of the current source; first means coupled to the diodes for selectively reverse biasing the diodes to cut off current flow therethrough; and second means coupled to the second leg for selectively controlling current flow therethrough; and the first and second means being adapted such that current can essentially only flow through one circuit leg or the other circuit leg.

Claim 25

A track/hold circuit comprising: first and second circuit legs; an essentially constant current source coupled to the first and second circuit legs; the first circuit leg comprises first, second, third and fourth diodes configured as a Wheatstone bridge; a track/hold circuit input terminal being coupled to the cathode of the first diode and to the anode of the second diode; a track/hold circuit output terminal being coupled to the cathode of the third diode, to the anode of the fourth diode and to a first terminal of a capacitor; the anodes of the first and third diodes being coupled together at a first node and said first node being coupled via the conduction path of a first transistor to a first portion of the current source; the cathodes of the third and fourth diodes being coupled together at a second node and said second node being coupled via the conduction path of a second transistor to a second portion of the current source; first means coupled to the diodes for selectively reverse biasing the diodes to cut off current flow therethrough; and second means coupled to the second leg for selectively controlling current flow therethrough; and the first and second means being adapted such that current can essentially only flow through one circuit leg or the other circuit leg.

Claim 26

Circuitry comprising: first, second and third circuit legs; a current source coupled to the first, second and third circuit legs; first storage means coupled to a first circuitry output terminal for storing information appearing at the first circuitry output terminal for a useful period of time; second storage means coupled to a second circuitry output terminal for storing information appearing at the second circuitry output terminal for a useful period of time; the first circuit leg comprises first, second, third and fourth diodes configured as a Wheatstone bridge with the cathode of the first diode and the anode of the second diode being coupled to a first circuitry input terminal and with the first circuitry output terminal being coupled to the cathode of the third diode and to the anode of the fourth diode; the anodes of the first and third diode being coupled together; the cathodes of the third and fourth diodes being coupled together; the second circuit leg comprises fifth, sixth, seventh and eighth diodes configured as a Wheatstone bridge with the cathode of the fifth diode and the anode of the sixth diode being coupled to a second circuitry input terminal and with the second circuitry output terminal being coupled to the cathode of the seventh diode and to the anode of the eighth diode; the anodes of the fifth and seventh diodes being coupled together; the cathodes of the sixth and eighth diodes being coupled together; and control means for controlling current flow through the first, second and third circuit legs such that current can flow essentially through only one selected circuit leg at a time.

Claim 27

Circuitry comprising: first, second and third circuit legs; a current source coupled to the first, second and third circuit legs; first storage means coupled to a first circuitry output terminal for storing information appearing at the first circuitry output terminal for a useful period of time; second storage means coupled to a second circuitry output terminal for storing information appearing at the second circuitry output terminal for a useful period of time; the first circuit leg comprises first, second, third and fourth diodes configured as a Wheatstone bridge with the cathode of the first diode and the anode of the second diode being coupled to a first circuitry input terminal and with the first circuitry output terminal being coupled to the cathode of the third diode and to the anode of the fourth diode; the anodes of the first and third diode being coupled together; the cathodes of the third and fourth diodes being coupled together; the second circuit leg comprises fifth, sixth, seventh and eighth diodes configured as a Wheatstone bridge with the cathode of the fifth diode and the anode of the sixth diode being coupled to a second circuitry input terminal and with the second circuitry output terminal being coupled to the cathode of the seventh diode and to the anode of the eighth diode; the anodes of the fifth and seventh diodes being coupled together; the cathodes of the sixth and eighth diodes being coupled together; and control means for controlling current flow through the first, second and third circuit legs such that current can flow essentially through only one selected circuit leg at a time.

Claim 28

The circuitry of claim 22 wherein: the first circuit leg comprises a first transmission gate having a first terminal coupled to the anodes of the first and third diodes and further comprises a second transmission gate having a first terminal coupled to the cathodes of the second and fourth diodes; and the second circuit leg comprises a third transmission gate having a first terminal coupled to the anodes of the fifth and seventh diodes and further comprises a fourth transmission gate having a first terminal coupled to the cathodes of the sixth and eighth diodes.

Claim 29

The circuitry of claim 23 wherein: the third circuit leg comprises a first MOS transistor having first and second output terminals and a gate terminal; and all of the diodes are Schottky barrier diodes.

Claim 30

The circuitry of claim 24 further comprising: second and third MOS transistors each having first and second output terminals and a gate terminal; second terminals of the first and second transmission gates being coupled to the first output terminal of the second transistor; second terminals of the third and fourth transmission gates being coupled to the first output terminal of the third transistor; ninth and tenth diodes; the cathode of the ninth diode being coupled to the second output terminal of the second transistor; and the anode of the tenth diode being coupled to the second output terminal of th third transistor.

Claim 31

The circuitry of claim 25 wherein the ninth and tenth diodes are Schottky barrier diodes.

Claim 32

The circuitry of claim 26 wherein: the current source is an essentially constant current source which comprises fourth and fifth MOS transistors each having first and second output terminals and a gate terminal; the first output terminal of the fourth transistor being coupled to the anode of the ninth diode and to the first output terminal of the first transistor; and the first output terminal of the fifth transistor being coupled to the second output terminal of the first transistor and to the cathode of the tenth diode.

Claim 33

The circuitry of claim 26 wherein: the constant current source further comprises sixth and seventh MOS transistors, which are of the same conductivity type as the second and fourth transistors, eighth and ninth MOS transistors, which are of the same conductivity type as the third and fifth transistors, eleventh and twelfth Schottky barrier diodes; the sixth, seventh, eighth and ninth transistors each having first and second output terminals and a gate terminal; the first output terminals of the fourth and sixth transistors being coupled together; the gate terminals of the fourth and sixth transistors being coupled to the second output terminal of the sixth transistor and to the anode of the eleventh diode; the cathode of the eleventh diode being coupled to the first output terminal of the seventh transistor; the second output terminal and the gate terminal of the seventh transistor being coupled to the gate terminal and the first output terminal of the eighth transistor and to the gate terminals of the second and third transistors; the second output terminal of the eighth transistor being coupled to the gate terminals of the fifth and ninth transistors and to the first output terminal of the ninth transistor; and the second output terminals of the fifth and ninth transistors being coupled together.

Claim 34

The circuitry of claim 28 wherein each of the transmission gates comprises a complementary pair of MOS transistors with first output terminals of both transistors being coupled together and being coupled to a first terminal of each transmission gate and with second output terminals of both transistors being coupled together and being coupled to a second terminal of each transmission gate.