Switch turn off circuitry for semiconductor bridge

Claim 2

An electronic switch comprising a semiconductor bridge having first and second signaling terminals, and bias control terminals; semiconductor circuit means activatable for connecting electrical voltages to said control terminals for forward biasing said bridge to effect a transmission of electrical information signals between said first and second terminals and deactivatable in response to a receipt of an instruction signal, and semiconductor means activated in response to a receipt of said instruction signal for concurrently cooperating with said circuit means upon its deactivation for reversing the connections of said voltages to said control terminals to reverse bias said bridge to interrupt said information signal transmitting between said first and second terminals.

Claim 3

The invention of claim 1 wherein said reversing semiconductor means comprises a pair of switching circuits activated by said semiconductor circuit means upon its deactivation for concurrently reversing the connection of said voltages through prescribed impedances to said control terminals.

Claim 4

For use with a semiconductor bridge having first and second signaling terminals and bias control terminals, means connected to said control terminals for switching said bridge into forward and reverse biased conditions to control the transmission of electrical information signals between said first and second terminals, and comprising first transistor circuit means activated in response to a receipt of an instruction signal for concurrently applying currents to said control terminals for forward biasing said bridge to transmit said information signals between said first and second terminals, and second transistor circuit means responsive to a deactivation of said applying means for concurrently connecting voltages to said control terminals during the entire interval between successive activations of said applying means for reverse biasing said bridge to interrupt said information signal transmitting between said first and second terminals.

Claim 5

For use with a semiconductor bridge having first and second signaling terminals and bias control terminals, means connected to said control terminals for switching said bridge into forward and reverse biased conditions to control the transmission of electrical information signals between said first and second terminals, and comprising first transistor circuit means activated in response to a receipt of an instruction signal for concurrently applying currents to said control terminals for forward biasing said bridge to transmit said information signals between said first and second terminals, and second transistor circuit means responsive to a deactivation of said applying means for concurrently connecting voltages to said control terminals during the entire interval between successive activations of said applying means for reverse biasing said bridge to interrupt said information signal transmitting between said first and second terminals.

Claim 6

For use with a semiconductor bridge having first and second signaling terminals, bias control terminals and first and second electrical voltages for bias control of said bridge, transistor means activatable for connecting said electrical voltages to said bias control terminals for steady state reverse bias of said bridge, and switching means responsive during a receipt of an instruction signal for deactivating said transistor means and reversing the connection of said electrical voltages to said bias control terminals for forward biasing said bridge to enable a transmission of electrical information signals between said signaling terminals.

Claim 7

For use with a semiconductor bridge having first and second signaling terminals, bias control terminals and first and second electrical voltages for bias control of said bridge, transistor means activatable for connecting said electrical voltages to said bias control terminals for steady state reverse bias of said bridge, and switching means responsive during a receipt of an instruction signal for deactivating said transistor means and reversing the connection of said electrical voltages to said bias control terminals for forward biasing said bridge to enable a transmission of electrical information signals between said signaling terminals.

Claim 8

The invention of claim 4 wherein said transistor means comprises a pair of switch circuits activated by said switching means for connecting said electrical voltages to said bias control terminals for steady state reverse bias of said bridge, said switching means comprises a pair of transistor current sources and said bridge comprises an effective electrical capacitance chargeable during the reversing connection of said electrical voltages to said bias control terminals, and each said switch circuit comprises a transistor circuit having a prescribed impedance and being operated by one of said pair of transistor current sources for connecting a predetermined one of said electrical voltages through said impedance to an individual one of said bias control terminals for discharging said electrical capacitance.

Claim 9

The invention of claim 5 wherein said bias connecting means further comprises means activated by said electrical voltages for antisaturation control of the operations of said transistor circuits in each said switch circuit.

Claim 10

Control circuitry for use with a semiconductor bridge having first and second signaling terminals and bias control terminals, said circuitry comprising control means activated and deactivated in response to a receipt of instruction signals for respectively enabling and disabling said bridge to transmit electrical information signals between said signaling terminals, means conductive upon a deactivation of said control means for concurrently connecting steady state reverse bias voltages to said bias control terminals for the entire duration of said deactivation of said control means, wherein said connecting means comprises a pair of transistor circuits responsive to a deactivation of said control means for connecting said reverse bias voltages to said bias control terminals for the entire duration of said deactivation of said control means, and each of said pair of transistor circuits comprising: a first transistor having a base electrode connected to said control means for receiving control signals, a collector electrode connected to one of said reverse bias voltages, and an emitter electrode; a second transistor having an emitter electrode connected to said emitter electrode of said first transistor and a base and a collector electrode; a first resistor serially connecting said collector electrode of said second transistor and one of said bias control terminals; a second resistor serially connecting said base electrode of said second transistor and said one of said reverse bias voltages; a third resistor connected between said emitter and base electrodes of said second transistor; a third transistor having an emitter electrode connected to said base electrode of said second transistor, a base electrode connectable to a reference voltage, and a collector electrode; and another resistor for serially connecting said collector electrode of said third transistor with a source of potential.

Claim 11

Control circuitry for use with a semiconductor bridge having first and second signaling terminals and bias control terminals, said circuitry comprising control means activated and deactivated in response to a receipt of instruction signals for respectively enabling and disabling said bridge to transmit electrical information signals between said signaling terminals, means conductive upon a deactivation of said control means for concurrently connecting steady state reverse bias voltages to said bias control terminals for the entire duration of said deactivation of said control means, wherein said connecting means comprises a pair of transistor circuits responsive to a deactivation of said control means for connecting said reverse bias voltages to said bias control terminals for the entire duration of said deactivation of said control means, and each of said pair of transistor circuits comprising: a first transistor having a base electrode connected to said control means for receiving control signals, a collector electrode connected to one of said reverse bias voltages, and an emitter electrode; a second transistor having an emitter electrode connected to said emitter electrode of said first transistor and a base and a collector electrode; a first resistor serially connecting said collector electrode of said second transistor and one of said bias control terminals; a second resistor serially connecting said base electrode of said second transistor and said one of said reverse bias voltages; a third resistor connected between said emitter and base electrodes of said second transistor; a third transistor having an emitter electrode connected to said base electrode of said second transistor, a base electrode connectable to a reference voltage, and a collector electrode; and another resistor for serially connecting said collector electrode of said third transistor with a source of potential.

Claim 12

The invention of claim 7 further comprising a pair of antisaturation circuits for controlling the turn on response of said bridge and the magnitude of conductive saturation of said pair of transistor circuits, and each of said pair of antisaturation circuits comprising a diode configured transistor and another transistor having an emitter electrode serially connected with said diode configured transistor to said collector electrode of said second transistor, and base and collector electrodes connectable to a source of reference potentials.