US5034927A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Read only memory
Assignee: Governor and Co of Bank of Scotland
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Filing: 1990-02-27
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Granted: 1991-07-23
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Expires: 2010-02-27
Abstract
Abstract A read only memory in which a portion of an address area thereof is allotted to that of another memory. The read only memory comprises at least one address decoding output circuit with a read only memory portion. The address decoding output circuit is formed to be programmable at the same time as the read only memory portion. Thus, an apparatus having this read only memory can be miniaturized and have a low power consumption, and the process of producing a system including this read only memory is simplified.
Inventors
- 👤 Yasushi Kasa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:31
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0638; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
174 words
A read only memory device comprising: a read only memory portion receiving an address signal and supplying stored data in response to the address signal; and an address decoding output circuit connected to said read only memory portion, said address decoding output circuit supplying a control signal to said read only memory portion to disable said read only memory portion when a predetermined address is detected and said address decoding output circuit supplying said control signal outside of said read only memory device to an external device to control said external device when said predetermined address is detected, wherein said read only memory portion and said address decoding output circuit are formed on a single chip and are programmable, said address decoding output circuit comprises decoders which are programmable logic circuits to be programmed to one of a circuit outputting the address signal, a circuit outputting the inverted address signal, and a circuit outputting a fixed level signal regardless of the address signal, and a logical gate for receiving the outputs of said decoders.
Claim 2
Dependent Claim
174 words
A read only memory device comprising: a read only memory portion receiving an address signal and supplying stored data in response to the address signal; and an address decoding output circuit connected to said read only memory portion, said address decoding output circuit supplying a control signal to said read only memory portion to disable said read only memory portion when a predetermined address is detected and said address decoding output circuit supplying said control signal outside of said read only memory device to an external device to control said external device when said predetermined address is detected, wherein said read only memory portion and said address decoding output circuit are formed on a single chip and are programmable, said address decoding output circuit comprises decoders which are programmable logic circuits to be programmed to one of a circuit outputting the address signal, a circuit outputting the inverted address signal, and a circuit outputting a fixed level signal regardless of the address signal, and a logical gate for receiving the outputs of said decoders.
Claim 3
Dependent Claim
108 words
A read only memory as set forth in claim 1, wherein said decoder comprises a first inverter, a second inverter, a first transistor connected between the input of the first inverter and the input of the second inverter, a second transistor connected between the output of the first inverter and the input of the second inverter, and a third transistor connected between the input of the second inverter and a power source, the gates of the first, second, and third transistors being supplied with a gate input signal, and one of the first, second, and third transistors being programmed to be conductive regardless of the gate input signal.
Claim 4
Dependent Claim
40 words
A read only memory as set forth in claim 1, wherein said address decoding output circuit is programmed simultaneously with said read only memory portion by connection or disconnection of transistors therein using a mask read only memory production process.
Claim 5
Dependent Claim
39 words
A read only memory as set forth in claim 1, wherein said address decoding output circuit is programmed simultaneously with said read only memory portion by ion implantation of transistors therein using a mask read only memory production process.
Claim 6
Dependent Claim
44 words
A read only memory as set forth in claim 1, wherein said address decoding output circuit is programmed simultaneously with said read only memory portion by forming or not forming a diffusion area in transistors therein using a mask read only memory production process.
Claim 7
Dependent Claim
45 words
A read only memory as set forth in claim 1, wherein said address decoding output circuit is programmed simultaneously with said read only memory portion by positive or negative charging of a floating gate of transistors therein using a programmable read only memory production process.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-22 | 1995-01-21 | 1995-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-22 | 1999-01-21 | 1999-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-22 | 2003-01-21 | 2003-07-23 | $7700.00 | Window Closed / Lapsed |