US4520464A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transparent instruction word bus memory system
Assignee: MagnaChip Semiconductor Ltd
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Filing: 1982-06-01
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Granted: 1985-05-28
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Expires: 2002-06-01
Abstract
Abstract A memory architecture for a single chip microprocessor or microcomputer in which instruction words have a greater bit length than the data words and the need exists for additional off-chip program memory. The instruction word lines from the off-chip program memory are coupled directly into the existing columns of a matrix on-chip, program memory ROM. Supplemental FETs are connected to selected rows and columns of the on-chip ROM and are operated in such a way that it is possible to either enable the on-chip ROM and decouple the off-chip instruction words, or to disable the on-chip ROM and couple the off-chip instruction words through the on-chip ROM.
Inventors
- 👤 John J. Hallauer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 02:38
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/268; G11; G11C; G11C8/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
92 words
A memory system, comprising: a matrix memory array having a set of row lines and a set of column lines; a source of instruction word signals; a source of address word signals; a row select coupled between the said source of address word signals and the row lines; a column select coupled between the said source of address word signals and the column lines; and means for disabling the row select in time coincidence with the transmission of instruction word signals from said source of instruction word signals to the column lines.
Claim 2
Dependent Claim
92 words
A memory system, comprising: a matrix memory array having a set of row lines and a set of column lines; a source of instruction word signals; a source of address word signals; a row select coupled between the said source of address word signals and the row lines; a column select coupled between the said source of address word signals and the column lines; and means for disabling the row select in time coincidence with the transmission of instruction word signals from said source of instruction word signals to the column lines.
Claim 3
Dependent Claim
32 words
The system recited in claim 1, further including means for disabling the transmission of instruction word signals from the column lines operable in time coincidence with the enabling of said row select.
Claim 4
Dependent Claim
21 words
The system recited in claim 2, wherein said source of instruction word signals is comprised of a separate addressable memory array.
Claim 5
Dependent Claim
54 words
The system recited in claim 3, further including: means for transmitting address word signals to said separate addressable memory array; and means for decoding the address word signals to synchronize the operation of said means for disabling the row select with the operation of said means for disabling the tranmission of instruction word signals.
Claim 6
Dependent Claim
31 words
The system recited in claim 4, wherein the column lines are grouped into sections, and at least one section has both a column select and an instruction word bit output line.
Claim 7
Dependent Claim
20 words
The system recited in claim 5, wherein the instruction word signals are coupled into sections having corresponding instruction word bits.
Claim 8
Dependent Claim
25 words
The system recited in claim 5, wherein: said means for disabling the row select is comprised of field effect transistors for grounding the row lines.
Claim 9
Dependent Claim
47 words
The system recited in claim 7, wherein: the instruction word signals and address word signals are multiplexed into a common bus joining said matrix memory array with said separate addressable memory array; and said matrix memory array and said separate addressable memory array are integrated circuit ROMs.
Claim 10
Dependent Claim
23 words
The system recited in claim 8, wherein said matrix array and said separate addressable memory array are located on separate integrated circuit chips.
References Cited (Backward Citations)
US3737879A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-27 | 1988-11-26 | 1989-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-27 | 1992-11-26 | 1993-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-27 | 1996-11-26 | 1997-05-28 | $7700.00 | Window Closed / Lapsed |