Controller integrated circuit

Claim 1

A controller integrated circuit, coupled to a peripheral unit, in a microcomputer system having a microprocessor, and to external control means, for controlling an operation of said peripheral unit, said external control means controls an operation of said peripheral unit other than said operation controlled by said controller integrated circuit, said controller integrated circuit comprising: an internal bus; a plurality of first registers coupled to said microprocessor via said internal bus for holding internal data; a selection circuit, coupled to said first registers, for selecting one or more of said first registers and for supplying the content of said selected one or more registers in accordance with a timing signal; timing signal generating means coupled to said selection circuit for generating said timing signal independently of said microprocessor during a period of time in which said controller integrated circuit does not affect control of said operation of said peripheral unit; a first external terminal coupled to said peripheral unit and to said external control means; output means coupled between said selection circuit and said first external terminal for supplying internal data in the first registers selected by said selection circuit to said first external terminal during said period in which said controller integrated circuit does not affect control of said peripheral unit; and a second external terminal connected to receive said timing signal from said timing signal generating means and supply said timing signal to said external control unit; wherein said external control means is coupled to said first external terminal and to said peripheral unit and includes means for generating a control signal in accordance with the internal data supplied from said output means to control said other operation of said peripheral unit.

Claim 4

A system including a microprocessor and a first bus coupled to said microprocessor, said system comprising: a second bus; a peripheral unit coupled to said second bus; a controller integrated circuit, including a first external terminal coupled to said first bus and a second external terminal coupled to said second bus, for controlling an operation of said peripheral unit, wherein said controller integrated circuit includes a register coupled to said first external terminal, signal generating means for generating a timing signal independently of said microprocessor for indicating a period of time in which said controller integrated circuit does not affect control of said operation of said peripheral unit, output means coupled to said register, to said second external terminal and to said signal generating means and responsive to said timing signal for providing data stored in said register to said second bus during said period of time, and a third external terminal connected to receive said timing signal from said signal generating means; and control means, coupled to said peripheral unit, to said second bus and to said third external terminal of said controller integrated circuit, for generating a control signal in accordance with the data provided to said second bus from said output means to control an operation of said peripheral unit other than said operation controlled by said controller integrated circuit.

Claim 5

A system including a microprocessor and a first bus coupled to said microprocessor, said system comprising: a second bus; a peripheral unit coupled to said second bus; a controller integrated circuit, including a first external terminal coupled to said first bus and a second external terminal coupled to said second bus, for controlling an operation of said peripheral unit, wherein said controller integrated circuit includes a register coupled to said first external terminal, signal generating means for generating a timing signal independently of said microprocessor for indicating a period of time in which said controller integrated circuit does not affect control of said operation of said peripheral unit, output means coupled to said register, to said second external terminal and to said signal generating means and responsive to said timing signal for providing data stored in said register to said second bus during said period of time, and a third external terminal connected to receive said timing signal from said signal generating means; and control means, coupled to said peripheral unit, to said second bus and to said third external terminal of said controller integrated circuit, for generating a control signal in accordance with the data provided to said second bus from said output means to control an operation of said peripheral unit other than said operation controlled by said controller integrated circuit.

Claim 6

A system including a microprocessor and a first bus coupled to said microprocessor, said system comprising: a second bus; a peripheral unit coupled to said second bus; a controller integrated circuit, coupled to said first bus and to said second bus, for controlling an operation of said peripheral unit, wherein said controller integrated circuit includes a plurality of data registers coupled to said microprocessor via said first bus for holding internal data, a first register for storing data for designating at least one of said plurality of data registers holding internal data, selection means coupled to said first register for selecting at least one of said plurality of data registers in response to the stored data in said first register, timing signal generating means for generating a timing signal independently of said microprocessor for indicating a period of time in which said second bus is not being used by said controller integrated circuit, and output means coupled to said selection means and to said timing signal generating means for providing the internal data in said selected at least one data register to said second bus during said period of time in which said second bus is not being used by said controller integrated circuit; and control means, coupled to said second bus, to said peripheral unit and to said controller integrated circuit, for generating a control signal in accordance with the internal data provided to said second bus from said output means to control an operation of said peripheral unit other than said operation controlled by said controller integrated circuit.

Claim 7

A system including a microprocessor and a first bus coupled to said microprocessor, said system comprising: a second bus; a peripheral unit coupled to said second bus; a controller integrated circuit, coupled to said first bus and to said second bus, for controlling an operation of said peripheral unit, wherein said controller integrated circuit includes a plurality of data registers coupled to said microprocessor via said first bus for holding internal data, a first register for storing data for designating at least one of said plurality of data registers holding internal data, selection means coupled to said first register for selecting at least one of said plurality of data registers in response to the stored data in said first register, timing signal generating means for generating a timing signal independently of said microprocessor for indicating a period of time in which said second bus is not being used by said controller integrated circuit, and output means coupled to said selection means and to said timing signal generating means for providing the internal data in said selected at least one data register to said second bus during said period of time in which said second bus is not being used by said controller integrated circuit; and control means, coupled to said second bus, to said peripheral unit and to said controller integrated circuit, for generating a control signal in accordance with the internal data provided to said second bus from said output means to control an operation of said peripheral unit other than said operation controlled by said controller integrated circuit.

Claim 10

A system including a microprocessor and a first bus coupled to said microprocessor, said system comprising: a second bus; a peripheral unit coupled to said second bus; a controller integrated circuit, including a first external terminal coupled to said first bus and a second external terminal coupled to said second bus, for controlling an operation of said peripheral unit, wherein said controller integrated circuit includes holding means, signal generating means for generating a timing signal independently of said microprocessor for indicating a period of time in which said controller integrated circuit does not affect control of said operation of said peripheral unit, output means coupled to said holding means, to said second external terminal and to said signal generating means and responsive to said timing signal for providing data stored in said holding means to said second bus during said period of time, and a third external terminal connected to receive said timing signal from said signal generating means; and control means, coupled to said peripheral unit, to said second bus and to said third external terminal of said controller integrated circuit, for generating a control signal in accordance with the data provided to said second bus from said output means to control an operation of said peripheral unit other than said operation controlled by said controller integrated circuit.

Claim 11

A system including a microprocessor and a first bus coupled to said microprocessor, said system comprising: a second bus; a peripheral unit coupled to said second bus; a controller integrated circuit, including a first external terminal coupled to said first bus and a second external terminal coupled to said second bus, for controlling an operation of said peripheral unit, wherein said controller integrated circuit includes holding means, signal generating means for generating a timing signal independently of said microprocessor for indicating a period of time in which said controller integrated circuit does not affect control of said operation of said peripheral unit, output means coupled to said holding means, to said second external terminal and to said signal generating means and responsive to said timing signal for providing data stored in said holding means to said second bus during said period of time, and a third external terminal connected to receive said timing signal from said signal generating means; and control means, coupled to said peripheral unit, to said second bus and to said third external terminal of said controller integrated circuit, for generating a control signal in accordance with the data provided to said second bus from said output means to control an operation of said peripheral unit other than said operation controlled by said controller integrated circuit.

Claim 12

A system including a microprocessor and a first bus coupled to said microprocessor, said system comprising: a second bus; a peripheral unit coupled to said second bus; a controller integrated circuit, including a first external terminal coupled to said first bus and a second external terminal coupled to said second bus, for controlling an operation of said peripheral unit, wherein said controller integrated circuit includes holding means coupled to said microprocessor via said first bus, signal generating means for generating a timing signal independently of said microprocessor for indicating a period in which said controller integrated circuit does not affect control of said operation of said peripheral unit, output means coupled to said holding means, to said second external terminal and to said signal generating means and responsive to said timing signal for providing data stored in said holding means to said second bus during said period, and a third external terminal connected to receive said timing signal from said signal generating means; and control means, coupled to said peripheral unit, to said second bus and to said third external terminal of said controller integrated circuit, for generating a control signal in accordance with the data provided to said second bus from said output means to control an operation of said peripheral unit other than said operation controlled by said controller integrated circuit.

Claim 13

A system including a microprocessor and a first bus coupled to said microprocessor, said system comprising: a second bus; a peripheral unit coupled to said second bus; a controller integrated circuit, including a first external terminal coupled to said first bus and a second external terminal coupled to said second bus, for controlling an operation of said peripheral unit, wherein said controller integrated circuit includes holding means coupled to said microprocessor via said first bus, signal generating means for generating a timing signal independently of said microprocessor for indicating a period in which said controller integrated circuit does not affect control of said operation of said peripheral unit, output means coupled to said holding means, to said second external terminal and to said signal generating means and responsive to said timing signal for providing data stored in said holding means to said second bus during said period, and a third external terminal connected to receive said timing signal from said signal generating means; and control means, coupled to said peripheral unit, to said second bus and to said third external terminal of said controller integrated circuit, for generating a control signal in accordance with the data provided to said second bus from said output means to control an operation of said peripheral unit other than said operation controlled by said controller integrated circuit.