Video signal processing apparatus with memory read/write timing related to horizontal scanning period

Claim 2

A video signal processing apparatus comprising: (a) A memory capable of storing one field portion of a video signal which has one field composed of (i+1/2) horizontal scanning periods, said i being an integer; and (b) switching means for setting said memory alternately into a writing state and a reading state in a cycle which is shorter than one field period, a period of time for having said memory in the writing state being at a length longer than (i+l)/k horizontal scanning periods and being an integer times as long as the horizontal scanning period, a period of time for having said memory in the reading state being at a length shorter than i/k horizontal scanning periods and being an integer times as long as the horizontal scanning periods, said k being an odd number.

Claim 3

An apparatus according to claim 1, further comprising address control means for controlling writing and reading addresses of said memory, said address control means including an address counter which is arranged to be reset once per one field period.

Claim 4

An apparatus according to claim 2, wherein said address counter is arranged to be reset alternately at an interval of i horizontal scanning periods and at an interval of (i+1) horizontal scanning periods.

Claim 5

A video signal processing apparatus comprising: (a) A memory capable of storing one field portion of a video signal which has one field period composed of (i+1/2) horizontal scanning periods, said i being integer; and (b) switching means for setting said memory alternately into a writing state and a no-writing state in a cycle which is shorter than one field period, a period of time for having said memory in the writing state being at a length longer than (i+1)/k horizontal scanning periods and being an integer times as long as the horizontal scanning period, a period of time for having said memory in the no-writing state being at a length shorter than i/k horizontal scanning periods and being an integer times as long as the horizontal scanning period, said k being an odd number.

Claim 6

A video signal processing apparatus comprising: (a) A memory capable of storing one field portion of a video signal which has one field period composed of (i+1/2) horizontal scanning periods, said i being integer; and (b) switching means for setting said memory alternately into a writing state and a no-writing state in a cycle which is shorter than one field period, a period of time for having said memory in the writing state being at a length longer than (i+1)/k horizontal scanning periods and being an integer times as long as the horizontal scanning period, a period of time for having said memory in the no-writing state being at a length shorter than i/k horizontal scanning periods and being an integer times as long as the horizontal scanning period, said k being an odd number.

Claim 7

A video signal processing apparatus comprising: (a) a reproducing head arranged to reproduce a video signal from a tape-shaped recording medium which has the video signal received in many tracks formed in parallel; (b) transporting means for transporting said tape-shaped recording medium, said transporting means having a first mode in which said recording medium is transported to have said reproducing head trace said recording medium in parallel to said tracks and a second mode in which said recording medium is transported to have said reproducing head traverse one of said many tracks in a predetermined period; (c) a memory capable of storing one field portion of said video signal; and (d) switching means for setting said memory alternately into a writing state and a no-writing state in a cycle which is shorter than one field period, a period of time for having said memory in the writing state being at a length longer than said predetermined period and being an integer times as long as the horizontal scanning period. a period of time for having said memory in the no-writing state being at a length shorter than said predetermined period and being an integer times as long as the horizontal scanning period.

Claim 8

A video signal processing apparatus comprising: (a) a reproducing head arranged to reproduce a video signal from a tape-shaped recording medium which has the video signal received in many tracks formed in parallel; (b) transporting means for transporting said tape-shaped recording medium, said transporting means having a first mode in which said recording medium is transported to have said reproducing head trace said recording medium in parallel to said tracks and a second mode in which said recording medium is transported to have said reproducing head traverse one of said many tracks in a predetermined period; (c) a memory capable of storing one field portion of said video signal; and (d) switching means for setting said memory alternately into a writing state and a no-writing state in a cycle which is shorter than one field period, a period of time for having said memory in the writing state being at a length longer than said predetermined period and being an integer times as long as the horizontal scanning period. a period of time for having said memory in the no-writing state being at a length shorter than said predetermined period and being an integer times as long as the horizontal scanning period.

Claim 9

An apparatus according to claim 5, wherein said many tracks on said recording medium are formed in such a manner that adjacent tracks among them are magnetized in different directions from each other.

Claim 10

An apparatus according to claim 5, wherein said transporting means transports said tape-shaped recording medium in said second mode at a speed (k+1) times as fast as in said first mode, said k being an odd number.

Claim 11

An apparatus according to claim 7, wherein said video signal has one field composed of (i+1/2) horizontal scanning periods, and wherein said switching means is arranged to set the period of time for having said memory in the writing state at a length longer than (i+1)/k horizontal scanning periods and to set the period of time for having said memory the no-writing state at a length shorter than (i/k) (horizontal scanning periods.

Claim 12

An apparatus according to claim 8, further comprising address control means for controlling writing and reading addresses of said memory, said address control means including an address counter which is arranged to be reset alternately at an interval of i horizontal scanning periods and at an interval of (i+1) horizontal scanning periods.