US5034635A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Positive to negative voltage translator circuit and method of operation
Assignee: Texas Instruments Inc
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Filing: 1990-03-30
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Granted: 1991-07-23
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Expires: 2010-03-30
Abstract
Abstract There is disclosed a circuit and method for converting on/off logic signals from one medium to on/off signals useful in a different medium. The circuit is particularly adapted to translate from positive voltage levels to negative voltage levels. The circuit includes voltage control levels for precisely controlling voltage as a function of temperature, all while only using positive voltage levels on the conversion circuit.
Inventors
- 👤 Timothy A. Ten Eyck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 09:19
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017509; H03K19/017518; H03K19/017527; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/30; H03K19/003; H03K19/00369; H03K19/00376
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
117 words
A circuit for converting from CMOS logic on/off input levels to ECL logic output levels, said circuit comprising an input for accepting on/off CMOS levels, first and second reference voltages each measured positive with respect to a ground level, and wherein said first reference level has a higher magnitude than said second reference level, a plurality of transistor switches operating from a voltage range between said ground and said first reference voltage magnitude, an output node having a negative resistive voltage potential thereon, a plurality of transistors connected between said first and said second reference voltage levels and said output node for controlling the provision of a selected one of said reference levels to said output node.
Claim 2
Dependent Claim
117 words
A circuit for converting from CMOS logic on/off input levels to ECL logic output levels, said circuit comprising an input for accepting on/off CMOS levels, first and second reference voltages each measured positive with respect to a ground level, and wherein said first reference level has a higher magnitude than said second reference level, a plurality of transistor switches operating from a voltage range between said ground and said first reference voltage magnitude, an output node having a negative resistive voltage potential thereon, a plurality of transistors connected between said first and said second reference voltage levels and said output node for controlling the provision of a selected one of said reference levels to said output node.
Claim 3
Dependent Claim
29 words
The circuit set forth in claim 1 wherein said output node reference voltage provision includes at least one resistive voltage drop and a plurality of precisely controlled voltages drops.
Claim 4
Dependent Claim
25 words
The circuit set forth in claim 2 wherein each said precisely controlled voltage drop is the voltage drop of a transistor base to emitter junction.
Claim 5
Dependent Claim
90 words
The circuit set forth in claim 3 wherein first and second transistors of said transistor switches are connected with their emitters connected in common and with their collectors connected in common and with the base of said second transistor connected to said second reference voltage and with the base of said first transistor connected to said first reference voltage and to said input so as to receive said on/off logic levels thereby providing one or the other of said reference voltage levels to said output node via said voltage drops.
Claim 6
Dependent Claim
53 words
The circuit set forth in claim 4 wherein said circuit further comprises an input control circuit including a plurality of transistor switches operable for switching onto said base of said first transistor either said first reference voltage or said ground in response to the application of said on or off input signal, respectively.
Claim 7
Dependent Claim
23 words
The circuit set forth in claim 5 wherein at least two transistors of said input control circuit are always in the on condition.
Claim 8
Dependent Claim
126 words
A circuit for converting from a first set of logical on/off input voltage levels to a second set of logical on/off output voltage levels, said circuit comprising an input for accepting on/off logic levels, first and second reference voltages each measured positive with respect to a ground level, and wherein said first reference level has a higher magnitude than said second reference level, a plurality of electronic switches operating from a voltage range between said ground and said first reference voltage magnitude, an output node having a negative resistive voltage potential thereon, a plurality of switches connected between said first and said second reference voltage levels and said output node for controlling the provision of a selected one of said reference levels to said output node.
Claim 9
Dependent Claim
126 words
A circuit for converting from a first set of logical on/off input voltage levels to a second set of logical on/off output voltage levels, said circuit comprising an input for accepting on/off logic levels, first and second reference voltages each measured positive with respect to a ground level, and wherein said first reference level has a higher magnitude than said second reference level, a plurality of electronic switches operating from a voltage range between said ground and said first reference voltage magnitude, an output node having a negative resistive voltage potential thereon, a plurality of switches connected between said first and said second reference voltage levels and said output node for controlling the provision of a selected one of said reference levels to said output node.
Claim 10
Dependent Claim
29 words
The circuit set forth in claim 7 wherein said output node reference voltage provision includes at least one resistive voltage drop and a plurality of precisely controlled voltages drops.
Claim 11
Dependent Claim
25 words
The circuit set forth in claim 8 wherein each said precisely controlled voltage drop is the voltage drop of a transistor base to emitter junction.
Claim 12
Dependent Claim
90 words
The circuit set forth in claim 9 wherein said switches are transistors, a first and second of said transistors connected with their emitters in common and with their collectors in common and with the base of said second one connected to said second reference voltage and with the base of said first one connected to aid first reference voltage and to said input so as to receive said on/off logic levels thereby providing one or the other of said reference voltage levels to said output node via said voltage drops.
Claim 13
Dependent Claim
51 words
The circuit set forth in claim 10 wherein said circuit further comprises an input control circuit including a plurality of transistor switches operable for switching onto said base of said first transistor either said first reference voltage or said ground in response to the application of said on/off logic levels, respectively.
Claim 14
Dependent Claim
25 words
The circuit set forth in claim 11 wherein at least two of said transistors of said input control circuit are always in the "on" condition.
Claim 15
Independent Claim
123 words
The method for converting from CMOS logic on/off input levels to ECL logic output levels, said method comprising the steps of establishing first and second reference voltages each measured positive with respect to a ground level, and wherein said first reference level has a higher magnitude than said second reference level, operating a plurality of transistor switches from a voltage range between said ground and said first reference voltage magnitude, establishing an output node having a negative resistive voltage potential thereon, connecting a plurality of transistors between said first and said second reference voltage levels and said output node, and controlling the provision of a selected one of said reference levels to said output node under control of said connected plurality of transistors.
Claim 16
Independent Claim
123 words
The method for converting from CMOS logic on/off input levels to ECL logic output levels, said method comprising the steps of establishing first and second reference voltages each measured positive with respect to a ground level, and wherein said first reference level has a higher magnitude than said second reference level, operating a plurality of transistor switches from a voltage range between said ground and said first reference voltage magnitude, establishing an output node having a negative resistive voltage potential thereon, connecting a plurality of transistors between said first and said second reference voltage levels and said output node, and controlling the provision of a selected one of said reference levels to said output node under control of said connected plurality of transistors.
Claim 17
Dependent Claim
27 words
The method set forth in claim 13 where said output node step includes at least one resistive voltage drop and a plurality of precisely controlled voltages drops.
Claim 18
Dependent Claim
25 words
The method set forth in claim 14 wherein each said precisely controlled voltage drop is the voltage drop of a transistor base to emitter junction.
Claim 19
Dependent Claim
95 words
The method set forth in claim 15 wherein said transistor connecting step includes connecting a first and second of said transistors with their emitters connected in common and with their collectors connected in common and with the base of said second one connected to said second reference voltage and with the base of said first one connected to said first reference voltage and to an input node so as to receive said input on/off logic levels thereby providing one or the other of said reference voltage levels to said output node via said voltage drops.
Claim 20
Dependent Claim
59 words
The method set forth in claim 16 wherein said transistor connecting step further comprises the step of establishing an input control circuit including a plurality of transistor switches operable for switching onto said base of said first transistor either said first referenced voltage or said ground in response to the application of said on or off input signal, respectively.
Claim 21
Dependent Claim
20 words
The method set forth in claim 17 wherein at least two of said transistors are always in the one condition.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-07-22 | 1995-01-21 | 1995-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-22 | 1999-01-21 | 1999-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-22 | 2003-01-21 | 2003-07-23 | $7700.00 | Window Closed / Lapsed |