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US5032743A Expired / Lapsed US ⏱️ 0.0 years remaining

Skew clamp

Assignee: Fairchild Semiconductor Corp
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Filing: 1990-05-09
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Granted: 1991-07-16
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Expires: 2010-05-09
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Abstract

Abstract A circuit is described for reducing the skew between a pair of signal lines in a digital system. Before the two lines display a change in signal the circuit senses whether the signals are similar or different. If similar, the two lines are clamped together in true fashion. If different, the two lines are clamped together complementarily such that the signals remain mutually inverted.

Inventors

  • 👤 Alan C. Rogers

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 19:36
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15006

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 59 words
A circuit for reducing the skew between digital signals which appear on a pair of lines in a digital system, said circuit comprising: means for determining whether said digital signals are true or complementary to each other; and means for coupling said pair of lines together in true fashion when said signals are determined to have a true relationship.
Claim 2
Dependent Claim 59 words
A circuit for reducing the skew between digital signals which appear on a pair of lines in a digital system, said circuit comprising: means for determining whether said digital signals are true or complementary to each other; and means for coupling said pair of lines together in true fashion when said signals are determined to have a true relationship.
Claim 3
Dependent Claim 59 words
A circuit for reducing the skew between digital signals which appear on a pair of lines in a digital system, said circuit comprising: means for determining whether said digital signals are true or complementary to each other; and means for coupling said pair of lines together in complementary fashion when said signals are determined to have a complementary relationship.
Claim 4
Dependent Claim 59 words
A circuit for reducing the skew between digital signals which appear on a pair of lines in a digital system, said circuit comprising: means for determining whether said digital signals are true or complementary to each other; and means for coupling said pair of lines together in complementary fashion when said signals are determined to have a complementary relationship.
Claim 5
Dependent Claim 124 words
A circuit for reducing the skew between digital signals which appear on a pair of lines in a digital system, said circuit comprising: first means coupled between said pair of lines for forcing said digital signals to the same potential in response to a true stimulus; second means coupled between said pair of lines for forcing said digital signals to complementary potentials in response to a complementary stimulus; means for predicting changes in the levels of said signals on said pair of lines; means for sensing the levels of the signals on said pair of lines; and means for generating a true stimulus when said signals on said pair of lines are to change and when said signals are to be at equal levels.
Claim 6
Dependent Claim 124 words
A circuit for reducing the skew between digital signals which appear on a pair of lines in a digital system, said circuit comprising: first means coupled between said pair of lines for forcing said digital signals to the same potential in response to a true stimulus; second means coupled between said pair of lines for forcing said digital signals to complementary potentials in response to a complementary stimulus; means for predicting changes in the levels of said signals on said pair of lines; means for sensing the levels of the signals on said pair of lines; and means for generating a true stimulus when said signals on said pair of lines are to change and when said signals are to be at equal levels.
Claim 7
Dependent Claim 35 words
The circuit of claim 3 further comprising means for generating a complementary stimulus when said signals on said pair of lines are to change and when said two signals are to be at different levels.
Claim 8
Dependent Claim 18 words
The circuit of claim 3 wherein said first means comprise a switch coupled between said pair of lines.
Claim 9
Dependent Claim 15 words
The circuit of claim 5 wherein said switch is composed of a CMOS transmission gate.
Claim 10
Dependent Claim 56 words
The circuit of claim 3 wherein said second means comprises a first inverter and first series switch coupled between said pair of lines, a second inverter and second series switch coupled in back-to-back relationship with said first inverter and first switch and means for operating said first and second switches in synchronism by said complementary stimulus.
Claim 11
Dependent Claim 16 words
The circuit of claim 7 wherein said first and second series switches are CMOS transmission gates.
Claim 12
Dependent Claim 46 words
The circuit of claim 4 wherein said pair of lines is driven from function generating circuits that provide the digital signals and said means for predicting changes in the levels and means for sensing the levels of said signals are incorporated into said function generating circuits.

References Cited (Backward Citations)

US4250410A Cited
US4661721A Cited
US4689496A Cited
US4700346A Cited
US4645947A Cited
US4737971A Cited
US4871931A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-07-15 1995-01-14 1995-07-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-07-15 1999-01-14 1999-07-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-07-15 2003-01-14 2003-07-16 $7700.00 Window Closed / Lapsed

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