Power saving arrangement and power saving method

Claim 1

A power saving arrangement for use in a subsidiary unit which communicates with a base unit in response to the detection of an ID signal leading data signal which are produced from said base unit and received by said subsidiary unit, said power saving arrangement comprising: power control circuit for selectively producing a full power and a reduced power; a processing circuit means for receiving and processing said data signal when the full power is applied thereto, and for detecting the level of the received signal when the reduced electric power is applied thereto; detecting circuit connected to said processing circuit means for detecting said data signal when the full power is applied thereto, and for detecting only said ID signal when the reduced power is applied thereto; first switching means for making and breaking a power supply path to said detecting circuit means from said power control circuit; and control means responsive to a signal representing the level of the received signal obtained from said processing means and also to said ID signal obtained from said detecting circuit means for controlling said power control circuit and said first switching means to establish either one of first standby mode, second standby mode and use mode such that: under the first standby mode, said first switching means breaks the power supply to said detecting circuit means and, at the same time, said power control circuit produces the reduced power to said processing circuit means, ready to detect the level of the received signal; under the second standby mode as established when said control means detects that the received signal level exceeds a predetermined level, said first switching means makes the power supply to said detecting circuit means and, at the same time, power control circuit produces the reduced power to said processing circuit means and also to said detecting circuit means, ready to detect and read the pattern of said ID signal; and under the use mode as established when said control means detects that said ID signal has a predetermined pattern, said first switching means makes the power supply to said detecting circuit means and, at the same time, power control circuit produces the full power to said processing circuit means and also to said detecting circuit means, ready to detect and read said data signal.