US5027370A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for the equalization of digital signals received in analog form
Assignee: Siemens AG
•
Filing: 1989-09-26
•
Granted: 1991-06-25
•
Expires: 2009-09-26
Abstract
Abstract A circuit arrangement for the equalization of digital signals received in analog form. The circuit arrangement is used in a digital signal receiving system for the equalization of digital signals received in analog form through an analog/digital converter which have been distorted by precursors and postcursors of subsequent or previously transmitted digital signals. In this case, the circuit arrangement includes a postcursor equalizer and a precursor equalizer connected with it that is designed as a transverse filter and multiplies a digital signal received at a sampling interval n by a main coefficient and, in addition, a predetermined number of digital signals immediately following the digital signal in question in each case by a predetermined secondary coefficient and sums that resulting product signal, with the aid of an adder, to a sum signal. In addition, the secondary coefficient immediately preceding the main coefficient is weighted with a predetermined factor and multiplied with a digital signal occurring at the scanning time n-1. A total sum signal is then formed, with the aid of the adder, from the resulting product signal and the first sum signal.
Inventors
- 👤 Heinrich Schenk
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:27
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03114; H04L25/03133
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
212 words
An arrangement for a digital signal receiving system for the equalization of digital signals received from an analog/digital converter of analog signals distorted by precursor effects and postcursor effects in the transmission of signals, comprising: precursor equalizer means coupled to post cursor equalizer means for equalization processing of the received digital signals, wherein said precursor equalizer means is in the form of a transversal filter connected with said postcursor equalizer means and receives successive digital signals at successive sampling intervals, and wherein said precursor equalizer means includes; first multiplier means for multiplying a first digital signal occurring at a sampling interval n by a main coefficient and each of a predetermined number of digital signals in sampling intervals (n+1), (n+2), . . . immediately following said first digital signal by respective subsidiary coefficients to provide first product signals, second multiplier means for multiplying the digital signal multiplied by the subsidiary coefficient, which is immediately following said first digital signal multiplied by said main coefficient, by a predetermined factor A and by a digital signal occurring at a sampling interval (n-1) to provide a second product signal, and adder means for providing a sum signal of said first product signals and said second product signal as an output of said precursor equalizer means.
Claim 2
Dependent Claim
212 words
An arrangement for a digital signal receiving system for the equalization of digital signals received from an analog/digital converter of analog signals distorted by precursor effects and postcursor effects in the transmission of signals, comprising: precursor equalizer means coupled to post cursor equalizer means for equalization processing of the received digital signals, wherein said precursor equalizer means is in the form of a transversal filter connected with said postcursor equalizer means and receives successive digital signals at successive sampling intervals, and wherein said precursor equalizer means includes; first multiplier means for multiplying a first digital signal occurring at a sampling interval n by a main coefficient and each of a predetermined number of digital signals in sampling intervals (n+1), (n+2), . . . immediately following said first digital signal by respective subsidiary coefficients to provide first product signals, second multiplier means for multiplying the digital signal multiplied by the subsidiary coefficient, which is immediately following said first digital signal multiplied by said main coefficient, by a predetermined factor A and by a digital signal occurring at a sampling interval (n-1) to provide a second product signal, and adder means for providing a sum signal of said first product signals and said second product signal as an output of said precursor equalizer means.
Claim 3
Dependent Claim
155 words
An arrangement according to claim 1, wherein said precursor equalizer means includes a plurality of first delay elements connected in series to which the successive digital signals are fed, wherein each of said first delay elements produces a delay time corresponding to a time interval between two successive sampling intervals and provides an output to a respective multiplier of said first multiplier means for multiplication by the respective one of said coefficients, and a second delay element receiving the digital signal multiplied by the subsidiary coefficient, which is immediately following said first digital signal multiplied by said main coefficient, which produces a delay time which is twice as long as the delay time of said first delay elements and provides an output to said second multiplier means for multiplication by said predetermined factor A, and the outputs of said first multiplier means and said second multiplier means are connected as inputs to said adder means.
Claim 4
Dependent Claim
143 words
An arrangement according to claim 1, wherein said first multiplier means includes a plurality of multipliers to which the successive digital signals are transmitted simultaneously, a first one of said multipliers having the main coefficient applied thereto and the other multipliers having the subsidiary coefficients applied thereto, respectively, and said multipliers have their outputs respectively connected as one of two inputs of a plurality of corresponding adders connected in series, and the second input of each adder receives an output of a previous adder through a delay element which produces a time delay corresponding to a time interval between two successive sampling intervals, except that a first adder, which receives the output of said first multiplier, receives as its second input the output of the multiplier immediately following said first multiplier which is multiplied by said factor A through said second multiplier means.
Claim 5
Dependent Claim
23 words
An arrangement according to claim 1, wherein the predetermined factor A is selected to have a value of one-half or a whole number.
Claim 6
Dependent Claim
23 words
An arrangement according to claim 2, wherein the predetermined factor A is selected to have a value of one-half or a whole number.
Claim 7
Dependent Claim
23 words
An arrangement according to claim 3, wherein the predetermined factor A is selected to have a value of one-half or a whole number.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-24 | 1994-12-24 | 1995-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-24 | 1998-12-24 | 1999-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-24 | 2002-12-24 | 2003-06-25 | $7700.00 | Window Closed / Lapsed |