Equalizer for the correction of digital signals

Claim 2

An equalizer for eliminating the effects of postcursor and precursor interference from a periodically sampled train of incoming digital signals, comprising: receiving means connected to a transmission path carrying said incoming signals; a first circuit branch connected to said receiving means, said first branch including first upstream filter means for converting a given signal sample into a first linearly prefiltered signal with at least partial suppression of postcursor effects, first threshold means connected to said first upstream filter means for deriving a first quantized pulse from said first prefiltered signal, first downstream filter means connected to said first threshold means for generating a precursor-compensating signal from said first quantized pulse, and first delay means connected in parallel with said first threshold means to said first upstream filter means for emitting a first retarded signal corresponding to said first prefiltered signal; a second circuit branch connected in parallel with said first circuit branch to said receiving means, said second branch including second upstream filter means for converting said given signal sample into a second linearly prefiltered signal with at least partial suppression of precursor effects, said second branch further including second delay means connected to said second upstream filter means for emitting a second retarded signal corresponding to said second prefiltered signal, the retardations introduced by said first and second delay means being identical and exceeding by one sampling period a lag introduced by the series combination of said first threshold means and said first downstream filter means; summing means with inputs connected to said first and second delay means and to said first downstream filter means for receiving said first and second retarded signals and said precursor-compensating signal therefrom; second threshold means connected to said summing means for deriving a second quantized pulse from the combination of signals received by said summing means; and second downstream filter means connected in a feedback loop between an output of said second threshold means and a further input of said summing means for delivering thereto a postcursor-compensating signal, derived from said second quantized pulse, with a delay of one sampling period.

Claim 3

An equalizer as defined in claim 1, further comprising: third downstream filter means connected to said second threshold means for generating another precursor-compensating signal from said second quantized pulse; third delay means in cascade with said first delay means for emitting a third retarded signal corresponding to said first prefiltered signal; fourth delay means in cascade with said second delay means for emitting a fourth retarded signal corresponding to said second prefiltered signal, the retardations introduced by said third and fourth delay means being identical and exceeding by one sampling period a lag introduced by the series combination of said summing means, said second threshold means and said third downstream filter means; adding means with inputs connected to said third and fourth delay means and to said third downstream filter means for receiving said third and fourth retarded signals and said other precursor-compensating signal therefrom; third threshold means connected to said adding means for deriving a third quantized pulse from the combination of signals received by said adding means; and fourth downstream filter means connected in a feedback loop between an output of said third threshold means and a further input of said adding means for delivering thereto another postcursor-compensating signal, derived from said third quantized pulse, with a delay of one sampling period.

Claim 4

An equalizer as defined in claim 2, further comprising fifth downstream filter means inserted between said first threshold means and an additional input of said adding means for delivering thereto yet a further precursor-compensating signal derived from said first quantized pulse, the retardation introduced by the cascaded first and third delay means exceeding by two sampling periods a lag introduced by the series combination of said first threshold means and said fifth downstream filter means.

Claim 5

An equalizer for eliminating the effects of postcursor and precursor interference from a periodically sampled train of incoming digital signals, comprising: receiving means connected to a transmission path carrying said incoming signals; a first circuit branch including first threshold means connected to said receiving means for deriving a first quantized pulse from a given signal sample, first downstream filter means connected to said first threshold means for generating a precursor-compensating signal from said first quantized pulse, and first delay means connected in parallel with said first threshold means to said receiving means for emitting a first retarded signal corresponding to said given signal sample; a second circuit branch connected in parallel with said first circuit branch to said receiving means, said second branch including upstream filter means for converting said given signal sample into a linearly prefiltered signal with at least partial suppression of precursor effects, said second branch further including second delay means connected to said upstream filter means for emitting a second retarded signal corresponding to said prefiltered signal, the retardation introduced by said first delay means exceeding by one sampling period a lag introduced by the series combination of said first threshold means and said first downstream filter means; summing means with inputs connected to said first and second delay means to said filter downstream filter means for receiving said first and second retarded signals and said precursor-compensating signal therefrom, the retardation introduced by said second delay means causing simultaneous arrival of said first and second retarded signals at said summing means; second threshold means connected to said summing means for deriving a second quantized pulse from the combination of signals received by said summing means; second downstream filter means connected in a feedback loop between an output of said second threshold means and a further input of said summing means for delivering thereto a postcursor-compensating signal, derived from said second quantized pulse, with a delay of one sampling period; third downstream filter means connected to said second threshold means for generating another precursor-compensating signal from said second quantized pulse; third delay means in cascade with said first delay means for emitting a third retarded signal corresponding to said given signal sample; fourth delay means in cascade with said second delay means for emitting a fourth retarded signal corresponding to said prefiltered signal, the retardations introduced by said third and fourth delay means being identical and exceeding by one sampling period a lag introduced by the series combination of said summing means, said second threshold means and said third downstream filter means; adding means with inputs connected to said third and fourth delay means and to said third downstream filter means for receiving said third and fourth retarded signals and said other precursor-compensating signal therefrom; third threshold means connected to said adding means for deriving a third quantized pulse from the combination of signals received by said adding means; and fourth downstream filter means connected in a feedback loop between an output of said third threshold means and a further input of said adding means for delivering thereto another postcursor-compensating signal, derived from said third quantized pulse, with a delay of one sampling period.

Claim 6

An equalizer for eliminating the effects of postcursor and precursor interference from a periodically sampled train of incoming digital signals, comprising: receiving means connected to a transmission path carrying said incoming signals; a first circuit branch including first threshold means connected to said receiving means for deriving a first quantized pulse from a given signal sample, first downstream filter means connected to said first threshold means for generating a precursor-compensating signal from said first quantized pulse, and first delay means connected in parallel with said first threshold means to said receiving means for emitting a first retarded signal corresponding to said given signal sample; a second circuit branch connected in parallel with said first circuit branch to said receiving means, said second branch including upstream filter means for converting said given signal sample into a linearly prefiltered signal with at least partial suppression of precursor effects, said second branch further including second delay means connected to said upstream filter means for emitting a second retarded signal corresponding to said prefiltered signal, the retardation introduced by said first delay means exceeding by one sampling period a lag introduced by the series combination of said first threshold means and said first downstream filter means; summing means with inputs connected to said first and second delay means to said filter downstream filter means for receiving said first and second retarded signals and said precursor-compensating signal therefrom, the retardation introduced by said second delay means causing simultaneous arrival of said first and second retarded signals at said summing means; second threshold means connected to said summing means for deriving a second quantized pulse from the combination of signals received by said summing means; second downstream filter means connected in a feedback loop between an output of said second threshold means and a further input of said summing means for delivering thereto a postcursor-compensating signal, derived from said second quantized pulse, with a delay of one sampling period; third downstream filter means connected to said second threshold means for generating another precursor-compensating signal from said second quantized pulse; third delay means in cascade with said first delay means for emitting a third retarded signal corresponding to said given signal sample; fourth delay means in cascade with said second delay means for emitting a fourth retarded signal corresponding to said prefiltered signal, the retardations introduced by said third and fourth delay means being identical and exceeding by one sampling period a lag introduced by the series combination of said summing means, said second threshold means and said third downstream filter means; adding means with inputs connected to said third and fourth delay means and to said third downstream filter means for receiving said third and fourth retarded signals and said other precursor-compensating signal therefrom; third threshold means connected to said adding means for deriving a third quantized pulse from the combination of signals received by said adding means; and fourth downstream filter means connected in a feedback loop between an output of said third threshold means and a further input of said adding means for delivering thereto another postcursor-compensating signal, derived from said third quantized pulse, with a delay of one sampling period.

Claim 7

An equalizer as defined in claim 4, further comprising fifth downstream filter means inserted between said first threshold means and an additional input of said adding means for delivering thereto yet a further precursor-compensating signal derived from said first quantized pulse, the retardation introduced by the cascaded first and third delay means exceeding by two sampling periods a lag introduced by the series combination of said first threshold means and said fifth downstream filter means.

Claim 8

An equalizer for eliminating the effects of postcursor and precursor interference from a periodically sampled train of incoming digital signals, comprising: receiving means connected to a transmission path carrying said incoming signals; a first circuit branch including first delay means connected to said receiving means for emitting a first retarded signal corresponding to a given signal sample; a second circuit branch connected in parallel with said first circuit branch to said receiving means, said second branch including upstream filter means for converting said given signal sample into a linearly prefiltered signal with at least partial suppression of precursor effects, said second branch further including second delay means connected to said upstream filter means for emitting a second retarded signal corresponding to said prefiltered signal; first summing means with inputs connected to said first and second delay means for receiving said first and second retarded signals, the retardations introduced by said first and second delay means causing simultaneous arrival of said first and second retarded signals at said first summing means; first threshold means connected to said first summing means for deriving a first quantized pulse from the combination of signals received by said first summing means; first downstream filter means connected in a feedback loop between an output of said first threshold means and a further input of said first summing means for delivering thereto a first postcursor-compensating signal, derived from said first quantized pulse, with a delay of one sampling period; second downstream filter means connected to said first threshold means for generating a precursor-compensating signal from said first quantized pulse; third delay means in cascade with said first delay means for emitting a third retarded signal corresponding to said given signal sample; fourth delay means in cascade with said second delay means for emitting a fourth retarded signal corresponding to said prefiltered signal, the retardations introduced by said third and fourth delay means being idenrical and exceeding by one sampling period a lag introduced by the series combination of said first summing means, said first threshold means and said second downstream filter means; second summing means with inputs connected to said third and fourth delay means and to said second downstream filter means for receiving said third and fourth retarded signals and said precursor-compensating signal therefrom; second threshold means connected to said second summing means for deriving a second quantized pulse from the combination of signals received by said second summing means; and third downstream filter means connected in a feedback loop between an output of said second threshold means and a further input of said second summing means for delivering thereto a second postcursor-compensating signal, derived from said second quantized pulse, with a delay of one sampling period.

Claim 9

An equalizer for eliminating the effects of postcursor and precursor interference from a periodically sampled train of incoming digital signals, comprising: receiving means connected to a transmission path carrying said incoming signals; a first circuit branch including first delay means connected to said receiving means for emitting a first retarded signal corresponding to a given signal sample; a second circuit branch connected in parallel with said first circuit branch to said receiving means, said second branch including upstream filter means for converting said given signal sample into a linearly prefiltered signal with at least partial suppression of precursor effects, said second branch further including second delay means connected to said upstream filter means for emitting a second retarded signal corresponding to said prefiltered signal; first summing means with inputs connected to said first and second delay means for receiving said first and second retarded signals, the retardations introduced by said first and second delay means causing simultaneous arrival of said first and second retarded signals at said first summing means; first threshold means connected to said first summing means for deriving a first quantized pulse from the combination of signals received by said first summing means; first downstream filter means connected in a feedback loop between an output of said first threshold means and a further input of said first summing means for delivering thereto a first postcursor-compensating signal, derived from said first quantized pulse, with a delay of one sampling period; second downstream filter means connected to said first threshold means for generating a precursor-compensating signal from said first quantized pulse; third delay means in cascade with said first delay means for emitting a third retarded signal corresponding to said given signal sample; fourth delay means in cascade with said second delay means for emitting a fourth retarded signal corresponding to said prefiltered signal, the retardations introduced by said third and fourth delay means being idenrical and exceeding by one sampling period a lag introduced by the series combination of said first summing means, said first threshold means and said second downstream filter means; second summing means with inputs connected to said third and fourth delay means and to said second downstream filter means for receiving said third and fourth retarded signals and said precursor-compensating signal therefrom; second threshold means connected to said second summing means for deriving a second quantized pulse from the combination of signals received by said second summing means; and third downstream filter means connected in a feedback loop between an output of said second threshold means and a further input of said second summing means for delivering thereto a second postcursor-compensating signal, derived from said second quantized pulse, with a delay of one sampling period.

Claim 10

An equalizer as defined in claim 6, further comprising a decision stage in said first branch, connected to said receiving means in parallel with said first delay means, and fourth downstream filter means inserted between said decision stage and an additional input of said second summing means for delivering thereto another precursor-compensating signal derived from the output of said decision stage, the retardation introduced by the cascaded first and third delay means exceeding by two sampling periods a lag introduced by the series combination of said decision stage and said fourth downstream filter means.