Zebra signal generating circuit of a video camera

Claim 2

A zebra signal generating circuit of a video camera, comprising: video signal amplifying means for generating amplified red, green, and blue video signals; non-additive mixing video signal means for outputting a non-additive mixing video signal proportional to an average value of the red, green, and blue video signals utilizing the amplified red, green, and blue video signals from said video signal amplifying means; video signal integrating means for amplifying and successively integrating the green video amplified signal of the red, green, and blue amplified signals from said video signal amplifying means; zebra signal generating means for generating comb teeth pattern signals in response to reception of a control signal from a control terminal; and zebra signal control means for comparing the zebra signal with a reference voltage and generating the zebra signal in stages by controlling and switching through a logic circuit.

Claim 3

A zebra signal generating circuit of a video camera according to claim 1, wherein: the non-additive mixing video signal generated from said non-additive mixing video signal means and the signal integrated by said video signal integrating circuit means are compared with a reference voltage by stages.

Claim 4

A zebra pattern video signal control circuit, comprising: a plurality of comparators, wherein a first one of said comparators compares a non-additive mixing video signal with an integrated amplified signal and generates a first compared difference signal, a second comparator compares said non-additive mixing video signal to a first reference voltage and generates a second compared difference signal, and a third comparator compares said non-additive mixing video signal to a second reference voltage and generates a third compared difference signal and a fourth comparator compares said non-additive mixing video signal to a third reference voltage and generates a fourth compared difference signal; multiple bit counter means having a clock and clock terminal connectable to receive a sub-carrier voltage, and generate a signal reduced to one quarter of the frequency of said sub-carrier voltage; control means for controlling said plurality of comparators and said multiple bit counter means in response to control signals; a plurality of AND gates wherein a first gate of said plurality of AND gates generates an AND logically multiplied signal from said second compared difference signal and from a first output signal from a band selector switch, a second gate of said plurality of AND gates generates an AND logically multiplied signal from said third compared difference signal and from said fourth compared difference signal and from a third output signal from said band selector switch, a third gate of said plurality of AND gates generates an AND logically multiplied signal from said fourth compared difference signal and from a fourth output signal from said band selector switch, and a fourth gate of said plurality of AND gates generates an AND logically multiplied signal from said second compared difference signal and from said third compared difference signal and from a second output signal from said band selector switch; said OR gate means, for logically summing signals generated from said plurality of AND gates; and switching means for changing a switch conductivity in response to said zebra signal and a signal generated from said OR gate means and said first compared difference signal.

Claim 5

A zebra pattern video signal control circuit, comprising: a plurality of comparators, wherein a first one of said comparators compares a non-additive mixing video signal with an integrated amplified signal and generates a first compared difference signal, a second comparator compares said non-additive mixing video signal to a first reference voltage and generates a second compared difference signal, and a third comparator compares said non-additive mixing video signal to a second reference voltage and generates a third compared difference signal and a fourth comparator compares said non-additive mixing video signal to a third reference voltage and generates a fourth compared difference signal; multiple bit counter means having a clock and clock terminal connectable to receive a sub-carrier voltage, and generate a signal reduced to one quarter of the frequency of said sub-carrier voltage; control means for controlling said plurality of comparators and said multiple bit counter means in response to control signals; a plurality of AND gates wherein a first gate of said plurality of AND gates generates an AND logically multiplied signal from said second compared difference signal and from a first output signal from a band selector switch, a second gate of said plurality of AND gates generates an AND logically multiplied signal from said third compared difference signal and from said fourth compared difference signal and from a third output signal from said band selector switch, a third gate of said plurality of AND gates generates an AND logically multiplied signal from said fourth compared difference signal and from a fourth output signal from said band selector switch, and a fourth gate of said plurality of AND gates generates an AND logically multiplied signal from said second compared difference signal and from said third compared difference signal and from a second output signal from said band selector switch; said OR gate means, for logically summing signals generated from said plurality of AND gates; and switching means for changing a switch conductivity in response to said zebra signal and a signal generated from said OR gate means and said first compared difference signal.

Claim 6

The circuit of claim 3, wherein said integrated amplified signal is generated from two integrating circuits and an amplifying circuit.

Claim 7

The circuit of claim 3, whereby said non-additive mixing video signal is generated from a plurality of transistors, wherein an amplified red video signal is an input on a base terminal of a first transistor of said plurality of transistors, an amplified green video signal is an input on a base terminal of a second transistor of said plurality of transistors, an amplified blue video signal is an input on a base terminal of a third transistor of said plurality of transistors; said non-additive mixing video signal is generated in response to said amplified red video signal and said amplified green video signal and said amplified blue video signal; and said non-additive mixing video signal is a voltage value proportional to the average value of said amplified red video signal and said amplified green video signal and said amplified blue video signal.