US5023615A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Large scale integrated circuit for converting pulse code modulated data to an analog signal
Assignee: Sony Corp
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Filing: 1990-02-20
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Granted: 1991-06-11
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Expires: 2010-02-20
Abstract
Abstract In a digital-to-analog converter for converting a received digital signal having N bits and a sampling frequency fs to an analog signal; digital interpolation filter receives the digital signal and generates a modified digital signal having a number of bits less than N and a sampling frequency greater than fs, pulse width modulator receives the modified digital signal and generates a pulse signal having pulse widths which correspond to the modified digital signal, output buffer having a complementary metal oxide semiconductor (CMOS) inverter circuit including P channel and N channel transistors having respective resistance values receives the pulse signal and low-pass filter receives the output signal from the output buffer, wherein the digital interpolation filter, the pulse width modulator and the output buffer are formed in an integrated circuit, and when the transistors are conductive the resistance values of the P channel and N channel transistors are set equal to each other by adjusting a voltage applied to the integrated circuit substrate so as to improve the signal-to-noise ratio of the produced analog signal.
Inventors
- 👤 Takaaki Yamada
- 👤 Kazutoshi Shimizume
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:41
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H10; H10W; H10W72/00; H10W72/90; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H03M1/82; H03M1/822; H10W72/50; H10W72/931; H10W72/932
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
205 words
In a digital-to analog converter for converting a received digital signal having N bits and a sampling frequency fs to an analog signal with an improved signal-to-noise ratio which comprises, digital interpolation filter means for receiving said digital signal and generating a modified digital signal having a number of bits less than N and a sampling frequency greater than fs, pulse width modulator means for receiving said modified digital signal and generating a pulse signal having pulse widths which correspond to said modified signal, output buffer means for receiving said pulse signal and having a complementary metal oxide semiconductor (CMOS) inverter circuit including P channel and N channel transistors having respective resistance values, and low-pass filter means for receiving an output signal from said output buffer means; said digital interpolation filter means, said pulse width modulator means and said output buffer means are formed in an integrated circuit which includes a substrate and means for receiving a variable supplied voltage through said substrate, and said supplied voltage is adjusted so that, when the transistors are conductive, the resistance values of said P channel and N channel transistors are made equal to each other so as to improve the signal-to-noise ratio of the produced analog signal.
Claim 2
Dependent Claim
205 words
In a digital-to analog converter for converting a received digital signal having N bits and a sampling frequency fs to an analog signal with an improved signal-to-noise ratio which comprises, digital interpolation filter means for receiving said digital signal and generating a modified digital signal having a number of bits less than N and a sampling frequency greater than fs, pulse width modulator means for receiving said modified digital signal and generating a pulse signal having pulse widths which correspond to said modified signal, output buffer means for receiving said pulse signal and having a complementary metal oxide semiconductor (CMOS) inverter circuit including P channel and N channel transistors having respective resistance values, and low-pass filter means for receiving an output signal from said output buffer means; said digital interpolation filter means, said pulse width modulator means and said output buffer means are formed in an integrated circuit which includes a substrate and means for receiving a variable supplied voltage through said substrate, and said supplied voltage is adjusted so that, when the transistors are conductive, the resistance values of said P channel and N channel transistors are made equal to each other so as to improve the signal-to-noise ratio of the produced analog signal.
Claim 3
Dependent Claim
105 words
A digital-to-analog converter according to claim 1; wherein said output buffer means includes a first CMOS inverter circuit for generating a first output signal, a second CMOS inverter circuit and a third CMOS inverter circuit connected in series for generating a second output signal, and in which said low-pass filter means includes a first low-pass filter supplied with said first output signal for generating a first filtered output signal, a second low-pass filter supplied with said second output signal for generating a second filtered output signal and a differential circuit supplied with said first and second filtered output signals for generating a differential output signal.
Claim 4
Dependent Claim
65 words
A digital-to-analog converter according to claim 1; wherein said integrated circuit includes first grounding means for grounding a first circuit portion which includes said digital interpolation filter means and said pulse width modulator means, second grounding means for grounding a second circuit portion which includes said output buffer means, and third grounding means for grounding a boundary portion between said first and second circuit portions.
Claim 5
Dependent Claim
17 words
A digital-to-analog converter according to claim 1; wherein said integrated circuit is a large scale integrated circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-10 | 1994-12-10 | 1995-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-10 | 1998-12-10 | 1999-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-10 | 2002-12-10 | 2003-06-11 | $7700.00 | Window Closed / Lapsed |