US5022007A
Expired / Lapsed
US
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Test signal generator for semiconductor integrated circuit memory and testing method thereof
Assignee: Mitsubishi Electric Corp
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Filing: 1990-04-10
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Granted: 1991-06-04
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Expires: 2010-04-10
Abstract
Abstract A test signal generator for a semiconductor integrated circuit memory, wherein when transfer transistors (20, 21, 14, 15) are rendered conductive, a test data cloumn is supplied from an I/O line pair (11, 12) to a column of a register (10) and stored therein. When a transfer (67) is rendered conductive, the test data column written in the register is written in a column of a memory cell (22) in the same pattern and when transfer transistors (16, 17) are rendered conductive, the test data column written in the register is inverted and the, written in the memory cell column, Data in the memory cell column is read out by a word line (13) and amplified by a sense amplifier (5), so that the data and the test data stored in the register are compared by a coincidence detection circuit 8 to detect whether it is coincident or not.
Inventors
- 👤 Kazutami Arimoto
- 👤 Yoshio Matsuda
- 👤 Tsukasa Ooishi
- 👤 Masaki Tsukude
- 👤 Kazuyasu Fujishima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:40
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
109 words
A test signal generator for a semiconductor integrated circuit memory having a plurality of bit line pairs, each pair including a first bit line (3) and a second bit line (4), comprising: a signal source (10) for outputting first and second voltages respectively corresponding to first and second logic levels, first switching means (14, 15) for selecting said first and second voltages outputted from said signal source and supplying the same to said first and second bit lines, and second switching means (16, 17) for selecting and inverting said first and second voltages outputted from said signal source and supplying the same to said first and second bit lines.
Claim 2
Dependent Claim
109 words
A test signal generator for a semiconductor integrated circuit memory having a plurality of bit line pairs, each pair including a first bit line (3) and a second bit line (4), comprising: a signal source (10) for outputting first and second voltages respectively corresponding to first and second logic levels, first switching means (14, 15) for selecting said first and second voltages outputted from said signal source and supplying the same to said first and second bit lines, and second switching means (16, 17) for selecting and inverting said first and second voltages outputted from said signal source and supplying the same to said first and second bit lines.
Claim 3
Dependent Claim
150 words
A test signal generator for a semiconductor integrated circuit memory according to claim 1, further comprising: a transfer gate (6, 9) for dividing each bit line of said plurality of bit line pairs (1, 2, 3, 4) into first and second nodes to connect memory cells (22) of said semiconductor integrated circuit memory to said first and second nodes, and wherein said signal source comprises register means for storing non-inverted and inverted logic level signals to the first nodes of said bit line pairs, said first switching means is connected so as to supply said non-inverted and inverted logic level signals stored in said register means to the respective first nodes of any of said bit line pairs, said second switching means is connected to supply said non-inverted and inverted logic level signals stored in said register means to the respective first nodes of any of said bit line pairs.
Claim 4
Dependent Claim
91 words
A test signal generator for a semiconductor integrated circuit memory according to claim 2, further comprising comparing means (8) for comparing the non-inverted and inverted logic level signal appearing on the first nodes of said bit line pairs with logic level signals appearing on the second nodes of said bit line pair, wherein said second switching means is connected between said comparing means and first nodes corresponding to bit lines of any of the bit line pairs corresponding to the non-inverted or inverted logic level signal stored in said register means.
Claim 5
Dependent Claim
53 words
A test signal generator for a semiconductor integrated circuit memory according to claim 3, further comprising: temporarily storing means (30) for temporarily storing a comparison output of said comparing means, and third switching means (31, 32) for outputting the comparison output temporarily stored in said temporarily storing means to said bit line pairs.
Claim 6
Dependent Claim
133 words
A test signal generator for a semiconductor integrated circuit memory having a bit line pair including first and second bit lines, a sense amplifier (5) connected to said bit line pair, a memory cell (22) connected to said bit line pair and a test circuit (8, 30) for testing a function of said memory cell, comprising: a signal source (10) for outputting first and second voltages respectively corresponding to first and second logic levels, first switching means (14, 15) for selecting said first and second voltages outputted from said signal source and supplying the same to said first and second bit lines, and second switching means (16, 17) for selecting and inverting said first and second voltages outputted from said signal source and supplying the same to said first and second bit lines.
Claim 7
Dependent Claim
133 words
A test signal generator for a semiconductor integrated circuit memory having a bit line pair including first and second bit lines, a sense amplifier (5) connected to said bit line pair, a memory cell (22) connected to said bit line pair and a test circuit (8, 30) for testing a function of said memory cell, comprising: a signal source (10) for outputting first and second voltages respectively corresponding to first and second logic levels, first switching means (14, 15) for selecting said first and second voltages outputted from said signal source and supplying the same to said first and second bit lines, and second switching means (16, 17) for selecting and inverting said first and second voltages outputted from said signal source and supplying the same to said first and second bit lines.
Claim 8
Dependent Claim
165 words
A testing method for testing a column of memory cells of a semiconductor integrated circuit memory by a test circuit contained therein, comprising the steps of: a first step for establishing at least either non-inverted or inverted logic level signals of a plurality of bits corresponding to the column of said semiconductor integrated circuit memory, a second step for temporarily storing at least either said established non-inverted or inverted logic level signals of the plurality of bits, a third step for reading the logic level signals stored in said second step, a fourth step for inverting the logic level signals read out in said third step, a fifth step for transferring said inverted logic level signals to said memory cell and storing the same, a sixth step for reading the logic level signals stored in said fifth step, and a seventh step for comparing the logic level signals read out in said sixth step with the logic level signals temporarily stored in said second step.
Claim 9
Dependent Claim
165 words
A testing method for testing a column of memory cells of a semiconductor integrated circuit memory by a test circuit contained therein, comprising the steps of: a first step for establishing at least either non-inverted or inverted logic level signals of a plurality of bits corresponding to the column of said semiconductor integrated circuit memory, a second step for temporarily storing at least either said established non-inverted or inverted logic level signals of the plurality of bits, a third step for reading the logic level signals stored in said second step, a fourth step for inverting the logic level signals read out in said third step, a fifth step for transferring said inverted logic level signals to said memory cell and storing the same, a sixth step for reading the logic level signals stored in said fifth step, and a seventh step for comparing the logic level signals read out in said sixth step with the logic level signals temporarily stored in said second step.
Claim 10
Dependent Claim
28 words
A testing method for a semiconductor integrated circuit memory according to claim 6, further comprising a eighth step for temporarily storing the comparison result in said seventh step.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-03 | 1994-12-03 | 1995-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-03 | 1998-12-03 | 1999-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-03 | 2002-12-03 | 2003-06-04 | $7700.00 | Window Closed / Lapsed |