Address control circuit for a video memory of a multi-image display video system

Claim 2

An address control circuit for a video memory of a multi-image display system comprising: means for supplying a video signal; a video memory for storing the video signal; a holding circuit for selectively holding write addresses of the video memory, and generating a held address value during a blanking period or a current address value during a video image period; and a bias generating circuit, responsive to the holding circuit, for positioning address areas of the video memory in which the video signal is stored.

Claim 3

An address control circuit according to claim 1, wherein the holding circuit includes an input address bus; a first comparator having a first input coupled to the input address bus, a second input coupled to a first comparison address, and an output for generating a signal indicating whether the input address equals the comparison address; a second comparator having a first input coupled to the input address bus, a second input coupled to a second comparison address, and an output for generating a signal indicating whether the input address equals the comparison address; a flip-flop having a set input coupled to the output of the first comparator, a reset input coupled to the output of the second comparator, and an output indicating whether the flip-flop is in the set state; and a latch having a data input bus coupled to the input address bus, a control input coupled to the output of the flip-flop, and an output address bus for generating a signal corresponding to the input address bus when the flip-flop is in the set state and for generating a signal corresponding to a latched value of the input bus when the flip-flop is in the reset state.

Claim 4

An address control circuit according to claim 2, wherein the bias generating circuit includes a bias generator having an output for generating an address bias value signal; an adder having a first input coupled to the output of the holding circuit, a second input coupled to the output of the bias generator, and an output.

Claim 5

The address control circuit according to claim 3 and further including means, responsive to the latch, for dividing the address bus signal by a factor, and generating a divided signal.

Claim 6

An address control circuit according to claim 4 wherein the bias generator includes means for generating a series of values, the difference between adjacent values being substantially equal to the ratio of the difference between the second comparison address and the first comparison address, to the factor.

Claim 7

An address control circuit according to claim 4 wherein the bias generator includes means for generating a series of values, the difference between adjacent values being substantially equal to a number greater than the ratio of the difference between the second comparison address and the first comparison address, to the factor.

Claim 8

An address control circuit according to claim 4, wherein the bias generating circuit includes means for generating a series of values, the difference between adjacent values varying with the image being currently processed.