US5021869A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Monolithic semiconductor chip interconnection technique and arrangement
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1988-12-27
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Granted: 1991-06-04
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Expires: 2008-12-27
Abstract
Abstract An interconnection arrangement and technique for a single semiconductor chip containing incomplete electric circuitry and having electric surface terminations permitting said incomplete electric circuitry to be externally interconnected, the interconnection arrangement being mountable on the semiconductor chip and capable of electically communicating with the semiconductor chip through electric surface terminations on the top surface of the semiconductor chip and on the bottom surface of the interconnection arrangement.
Inventors
- 👤 Ravindhar K. Kaw
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:26
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/67; H10W70/68; H10W70/685; H10W90/00; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
124 words
An integrated circuit, comprising: a semiconductor chip having a top surface; an incomplete electrical circuit integrated within the semiconductor chip; a pair of electrical surface terminations in a contiguous area on the top surface, each such surface termination electrically connected to a separate portion of said incomplete electrical circuit; an interconnection chip having a bottom surface sized to fit within the contiguous area; a pair of electrically interconnected surface terminations on the bottom surface; and means for mounting the interconnection chip on the semiconductor chip within the contiguous area so that each termination on the bottom surface is electrically connected to one of the surface terminations on the top surface, whereby the interconnection chip serves to complete the electrical circuit in the semiconductor chip.
Claim 2
Dependent Claim
124 words
An integrated circuit, comprising: a semiconductor chip having a top surface; an incomplete electrical circuit integrated within the semiconductor chip; a pair of electrical surface terminations in a contiguous area on the top surface, each such surface termination electrically connected to a separate portion of said incomplete electrical circuit; an interconnection chip having a bottom surface sized to fit within the contiguous area; a pair of electrically interconnected surface terminations on the bottom surface; and means for mounting the interconnection chip on the semiconductor chip within the contiguous area so that each termination on the bottom surface is electrically connected to one of the surface terminations on the top surface, whereby the interconnection chip serves to complete the electrical circuit in the semiconductor chip.
Claim 3
Dependent Claim
30 words
The integrated circuit claimed in claim 1, wherein the mounting means further comprises; bumps of electrically conducting material arranged for contact between surface terminations on the top and bottom surfaces.
Claim 4
Dependent Claim
20 words
The integrated circuit claimed in claim 2, wherein the surface terminations are treated to prevent leaching of the bump material.
Claim 5
Dependent Claim
13 words
The integrated circuit claimed in claim 2, wherein the bump material is solder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-03 | 1994-12-03 | 1995-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-03 | 1998-12-03 | 1999-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-03 | 2002-12-03 | 2003-06-04 | $7700.00 | Window Closed / Lapsed |