Patent US5019907A successfully refreshed from Google Patents.
US5019907A
Expired / Lapsed
US
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Pulse generating circuit
Assignee: Yamashita Denshi Sekkei KK
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Filing: 1989-12-05
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Granted: 1991-05-28
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Expires: 2009-12-05
Abstract
Abstract Horizontal synchronizing signals included in a video signal are inputted to a PLL circuit. A counter as a divider in the PLL circuit outputs signals which are synchronized with the horizontal synchronizing signals. A gate pulse generator counts the output pulses of counter and produces a control signal for controlling a phase comparator as one of elements of the PLL circuit. The operation of phase comparator is stopped in vertical intervals in accordance with the control signal so that the phase comparator is not affected by signals which are included in the video signal and are not synchronized with the horizontal synchronizing signals. Thus, the PLL circuit produces pulses which are synchronized with the horizontal synchronizing signals in a wide frequency range.
Inventors
- 👤 Satoshi Murakoshi
- 👤 Atsushi Sakurai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:41
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/12; H04N5/126
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
194 words
A pulse generating circuit comprising: a first generating circuit for generating signals in synchronism with horizontal synchronizing signals included in an inputted video signal; a second generating circuit for generating signals in synchronism with vertical synchronizing signals included in the inputted video signal; a PLL circuit comprising: a phase comparator have first and second input terminals, the first of which being connected to the output of the first generating circuit; a low-pass filter for smoothing the output of the phase comparator; a voltage controlled oscillator for generating pulses in accordance with the output of the low-pass filter; and a first counter for dividing the output of the voltage controlled oscillator and generating output signals which are applied to the second input terminal of the phase comparator; a third generating circuit for generating a control signal for controlling the phase comparator so that the operation of the phase comparator is inhibited at the time of a vertical interval; a second counter for counting the output of the first counter in one field; and an operating circuit for receiving the second counter output and producing as a output a signal for controlling the third generating circuit.
Claim 2
Dependent Claim
194 words
A pulse generating circuit comprising: a first generating circuit for generating signals in synchronism with horizontal synchronizing signals included in an inputted video signal; a second generating circuit for generating signals in synchronism with vertical synchronizing signals included in the inputted video signal; a PLL circuit comprising: a phase comparator have first and second input terminals, the first of which being connected to the output of the first generating circuit; a low-pass filter for smoothing the output of the phase comparator; a voltage controlled oscillator for generating pulses in accordance with the output of the low-pass filter; and a first counter for dividing the output of the voltage controlled oscillator and generating output signals which are applied to the second input terminal of the phase comparator; a third generating circuit for generating a control signal for controlling the phase comparator so that the operation of the phase comparator is inhibited at the time of a vertical interval; a second counter for counting the output of the first counter in one field; and an operating circuit for receiving the second counter output and producing as a output a signal for controlling the third generating circuit.
Claim 3
Dependent Claim
192 words
A pulse generating circuit comprising: a first generating circuit for generating signals in synchronism with horizontal synchronizing signals included in an inputted video signal; a second generating circuit for generating signals in synchronism with vertical synchronizing signals included in the inputted video signal; a PLL circuit comprising: a phase comparator having first and second input terminals, the first input terminal being connected to the output of the first generating circuit; a low-pass filter for smoothing the output of the phase comparator; a voltage controlled oscillator for generating pulses in accordance with the output of the low-pass filter; and a first counter for dividing the output of voltage controlled oscillator and generating output signals which are applied to the second input terminal of the phase comparator; and a third generating circuit for generating a control signal for controlling the phase comparator so that operation of the phase comparator is inhibited at the time of a vertical interval for gradually reducing the level of the output of the phase comparator in response to the control signal and to limit the output of the phase comparator to a specific level when the control signal terminates.
Claim 4
Dependent Claim
192 words
A pulse generating circuit comprising: a first generating circuit for generating signals in synchronism with horizontal synchronizing signals included in an inputted video signal; a second generating circuit for generating signals in synchronism with vertical synchronizing signals included in the inputted video signal; a PLL circuit comprising: a phase comparator having first and second input terminals, the first input terminal being connected to the output of the first generating circuit; a low-pass filter for smoothing the output of the phase comparator; a voltage controlled oscillator for generating pulses in accordance with the output of the low-pass filter; and a first counter for dividing the output of voltage controlled oscillator and generating output signals which are applied to the second input terminal of the phase comparator; and a third generating circuit for generating a control signal for controlling the phase comparator so that operation of the phase comparator is inhibited at the time of a vertical interval for gradually reducing the level of the output of the phase comparator in response to the control signal and to limit the output of the phase comparator to a specific level when the control signal terminates.
Claim 5
Dependent Claim
20 words
A pulse generating circuit according to claim 1, wherein the operating circuit controls the dividing rate of the first counter.
Claim 6
Dependent Claim
30 words
A pulse generating circuit according to claim 2, wherein the specific level corresponds to the output level of the phase comparator at the time when there are no phase errors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-27 | 1994-11-26 | 1995-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-27 | 1998-11-26 | 1999-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-27 | 2002-11-26 | 2003-05-28 | $7700.00 | Window Closed / Lapsed |