Patent US5019731A successfully refreshed from Google Patents.
US5019731A
Expired / Lapsed
US
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Analog switch circuit
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1989-05-08
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Granted: 1991-05-28
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Expires: 2009-05-08
Abstract
Abstract An analog switch circuit includes an input terminal to which an analog signal is supplied, an output terminal, first, second and third transistors, and a delay circuit. The first transistor has first and second electrodes and a gate, and the first electrode of the first transistor is connected to the input terminal. The second transistor has first and second electrodes and a gate, and the first electrode of the second transistor is coupled to the first electrode of the first transistor. The gate of the second transistor is supplied with a clock signal supplied from an external circuit. The delay circuit delays the clock signal by a predetermined time and generates a delayed clock signal supplied to the gate of the first transistor. The third transistor has first and second electrodes and a gate. The first and second electrodes of the third transistor are coupled to each other and to the second electrode of the second transistor and the output terminal through which an analog output signal is output. The gate of the third transistor is controlled so that the third transistor is turned ON when the second transistor is turned OFF.
Inventors
- 👤 Osamu Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:56
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/10; H03K17/102; G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; H03K17/687; H03K17/6871
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
198 words
An analog switch circuit, comprising: an input terminal to which an analog signal is supplied; an output terminal; a first transistor having first and second electrodes and a gate, the first electrode of said first transistor being connected to said input terminal; a second transistor having first and second electrodes and a gate, the first electrode of said second transistor being coupled to the second electrode of said first transistor, the gate of said second transistor being supplied with a clock signal; delay means operably connected between the gate of said first transistor and the gate of said second transistor, wherein said delay means is for delaying said clock signal by a predetermined time and generating a delayed clock signal supplied to the gate of said first transistor; and a third transistor having first and second electrodes and a gate, the first and second electrodes of said third transistor being coupled to each other and to the second electrode of said second transistor and said output terminal through which an analog output signal is output, the gate of said third transistor being controlled so that said third transistor is turned ON when said second transistor is turned OFF.
Claim 2
Dependent Claim
198 words
An analog switch circuit, comprising: an input terminal to which an analog signal is supplied; an output terminal; a first transistor having first and second electrodes and a gate, the first electrode of said first transistor being connected to said input terminal; a second transistor having first and second electrodes and a gate, the first electrode of said second transistor being coupled to the second electrode of said first transistor, the gate of said second transistor being supplied with a clock signal; delay means operably connected between the gate of said first transistor and the gate of said second transistor, wherein said delay means is for delaying said clock signal by a predetermined time and generating a delayed clock signal supplied to the gate of said first transistor; and a third transistor having first and second electrodes and a gate, the first and second electrodes of said third transistor being coupled to each other and to the second electrode of said second transistor and said output terminal through which an analog output signal is output, the gate of said third transistor being controlled so that said third transistor is turned ON when said second transistor is turned OFF.
Claim 3
Dependent Claim
34 words
An analog switch circuit as claimed in claim 1, wherein said first transistor has a source-drain breakdown voltage between the first and second electrodes thereof which is higher than that of said second transistor.
Claim 4
Dependent Claim
35 words
An analog switch circuit as claimed in claim 1, wherein said first transistor has a channel length longer than that of said second transistor, and a channel width wider than that of said second transistor.
Claim 5
Dependent Claim
37 words
An analog switch circuit as claimed in claim 1, wherein said first transistor and said second transistor are of an identical conduction type, and wherein said delay means comprises an even number of inverters connected in series.
Claim 6
Dependent Claim
36 words
An analog switch circuit as claimed in claim 1, wherein said first transistor is of a conduction type opposite to that of said second transistor, and wherein said delay means comprises an odd number of inverters.
Claim 7
Dependent Claim
41 words
An analog switch circuit as claimed in claim 1, wherein said delay means delays said clock signal so that said first transistor is turned OFF by applying said delayed clock signal applied thereto when said second transistor is completely cut off.
Claim 8
Dependent Claim
119 words
An analog switch circuit as claimed in claim 1, further comprising: a fourth transistor having first and second electrodes and a gate, the first and second electrodes of said fourth transistor being connected to each other and to the second electrode of said first transistor and the first electrode of said second transistor, the gate of said fourth transistor being controlled so that said fourth transistor is turned ON at the same time as said third transistor is turned ON; and a fifth transistor having a first electrode connected to the first and second electrodes of said third transistor, a second electrode connected to said output terminal, and a gate to which a fixed level signal is continuously applied.
Claim 9
Dependent Claim
23 words
An analog switch circuit as claimed in claim 7, wherein said fourth transistor is of almost the same size as said third transistor.
Claim 10
Dependent Claim
23 words
An analog switch circuit as claimed in claim 7, wherein said fifth transistor is of almost the same size as said first transistor.
Claim 11
Dependent Claim
38 words
An analog switch circuit as claimed in claim 7, wherein each of said first through fifth transistors is an N-channel transistor, and said fixed level signal applied to the gate of said fifth transistor is a high-level signal.
Claim 12
Dependent Claim
22 words
An analog switch circuit as claimed in claim 10, wherein said delay means comprises an even number of inverters connected in series.
Claim 13
Dependent Claim
52 words
An analog switch circuit as claimed in claim 7, wherein each of said first and fifth transistors is a P-channel transistor, and each of said second, third and fourth transistors is an N-channel transistor, and wherein said fixed level signal applied to the gate of said fifth transistor is a low-level signal.
Claim 14
Dependent Claim
19 words
An analog switch circuit as claimed in claim 12, wherein said delay means comprises an odd number of inverters.
Claim 15
Dependent Claim
32 words
An analog switch circuit as claimed in claim 12, wherein said delay means comprises an odd number of inverters, and said delayed signal is supplied to the gate of said third transistor.
Claim 16
Dependent Claim
115 words
An analog switch circuit as claimed in claim 7, further comprising: a sixth transistor having a first electrode being connected to a predetermined power source, a second electrode connected to the second electrode of said first transistor, the first and second electrodes of said fourth transistor, and a gate being controlled so that the second electrode of said first transistor is fixed to ground level when said first and second transistors are OFF; and a seventh transistor having a first electrode connected to the first and second electrodes of said third transistor and the first electrode of said fifth transistor, and having a second electrode and gate each being connected to said predetermined power source.
Claim 17
Dependent Claim
21 words
An analog switch circuit as claimed in claim 15, wherein each of said first through seventh transistors is an N-channel transistor.
Claim 18
Dependent Claim
45 words
An analog switch circuit as claimed in claim 15, wherein said sixth transistor fixes the second electrode of said first transistor, the first and second electrodes of said fourth transistor to a potential of said predetermined power source, when said sixth transistor is turned ON.
Claim 19
Dependent Claim
39 words
An analog switch circuit as claimed in claim 16, wherein said delay means comprises an even number of inverters series connected, and wherein said fixed level signal applied to the gate of said fifth transistor is a high-level signal.
Claim 20
Dependent Claim
24 words
An analog switch circuit as claimed in claim 1, wherein each of said first, second and third transistors is a metal oxide semiconductor transistor.
Claim 21
Dependent Claim
23 words
An analog switch circuit as claimed in claim 1, wherein each of said first, second and third transistors is a junction field-effect transistor.
Claim 22
Dependent Claim
44 words
An analog switch circuit as claimed in claim 1, further comprising an inverter inverting said clock signal to generate an inverted clock signal, which is supplied to the gate of said third transistor of a conduction type opposite to that of said first transistor.
Claim 23
Dependent Claim
30 words
An analog switch circuit as claimed in claim 1, wherein one of said first and third transistors is ON, when the other of said first and third transistors is OFF.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-27 | 1994-11-26 | 1995-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-27 | 1998-11-26 | 1999-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-27 | 2002-11-26 | 2003-05-28 | $7700.00 | Window Closed / Lapsed |