Patent US5019535A successfully refreshed from Google Patents.
US5019535A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Die attachment method using nonconductive adhesive for use in high density interconnected assemblies
Assignee: Lockheed Martin Corp
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Filing: 1989-03-28
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Granted: 1991-05-28
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Expires: 2009-03-28
Abstract
Abstract A method for grounding or electrically biasing an integrated circuit chip without using a conductive die attach material comprises affixing the chips to a substrate using a thermoplastic polyimide adhesive. A metallization layer electrically connects the sides of the chips, which act as grounding surfaces, to a biased or grounded conductive layer on the substrate. The top surfaces of the integrated circuit chips which include the interconnection pads are protected against undesired metallization by a removable protective layer while the metallization layer is applied. Metal electroplated on the metallization layer serves the functions of a heat sink for the chip and a ground plane between chips.
Inventors
- 👤 Robert J. Wojnarowski
- 👤 Charles W. Eichelberger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:09
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/614; H10W72/00; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/073; H10W72/07331; H10W72/07337; H10W72/30; H10W72/351; H10W72/353; H10W72/354; H10W72/50; H10W72/551; H10W72/552; H10W72/5524; Y; Y10; Y10S; Y10S438/00; Y10S438/976
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
96 words
A method of electrically connecting an integrated circuit chip to a ground or voltage bias, comprising the steps of: affixing said integrated circuit chip to a substrate with a nonconductive adhesive; protecting an electrically active area of said integrated chip from misapplied metallization by applying a removable layer of protective material over said electrically active area; coating said integrated circuit chip and said substrate with one layer of metallization, said layer of metallization providing an electrical connection from said integrated circuit chip to said ground or voltage bias; and removing said removable layer of protective material.
Claim 2
Independent Claim
96 words
A method of electrically connecting an integrated circuit chip to a ground or voltage bias, comprising the steps of: affixing said integrated circuit chip to a substrate with a nonconductive adhesive; protecting an electrically active area of said integrated chip from misapplied metallization by applying a removable layer of protective material over said electrically active area; coating said integrated circuit chip and said substrate with one layer of metallization, said layer of metallization providing an electrical connection from said integrated circuit chip to said ground or voltage bias; and removing said removable layer of protective material.
Claim 3
Dependent Claim
32 words
The method of claim 1 further comprising the step of electroplating a second layer of metallization on top of said one layer of metallization after the step of removing said removable layer.
Claim 4
Dependent Claim
59 words
The method of claim 2 further comprising the steps of applying a second removable layer over said electrically active area of said integrated circuit chip after said step of removing said removable layer and before the step of electroplating a second layer of metallization, and removing said second removable layer from said electrically active area after said electroplating step.
Claim 5
Dependent Claim
17 words
The method of claim 3 wherein each of said removable layers is comprised of a peelable tape.
Claim 6
Dependent Claim
56 words
The method of claim 1 further comprising the steps of ablating a portion of said one layer of metallization coated on top of said removable layer of protective material, and electroplating a second layer of metallization on top of said one layer of metallization prior to the step of removing said removable layer of protective material.
Claim 7
Dependent Claim
13 words
The method of claim 5 wherein said first removable layer comprises a photoresist.
Claim 8
Dependent Claim
13 words
The method of claim 5 wherein said first removable layer comprises a polyimide.
Claim 9
Dependent Claim
96 words
The method of claim 2 further comprising, between the coating and removing steps, the steps of: depositing a negative resist layer over said first layer of metallization; selectively exposing a portion of said negative resist positioned directly above said first removable layer of protective material; developing said negative resist layer to create a second removable layer of protective material where said negative resist layer has been exposed; electroplating a second layer of metallization on top of said one layer of metallization; removing said second removable layer of protective material; and etching said one layer of metallization.
Claim 10
Dependent Claim
60 words
The method of claim 2 further comprising, between the protecting and coating steps, the steps of applying a catalyst over said integrated circuit chip and said substrate, and destroying a portion of said catalyst present on said first removable layer of protective material, said coating step comprising empolying said catalyst to promote electroless deposition of said one layer of metallization.
Claim 11
Dependent Claim
10 words
The method of claim 9 wherein said catalyst comprises palladium.
Claim 12
Independent Claim
285 words
A method of connecting a first voltage level to a first integrated circuit chip and a second voltage level to a second integrated circuit chip wherein either voltage level may be ground, said first and second integrated circuit chips being affixed to a common substrate, said method comprising the steps of: affixing said first and second integrated circuit chips to said substrate with a nonconductive adhesive; protecting electrically active areas of said first and second integrated circuit chips and an area interposed therebetween on said substrate by applying first removable layers of protecting material over said areas; coating with a first metallization layer said first and second integrated circuit chips, said first removable layers of protecting material, and said common substrate; applying second removable layers of protecting material over said first metallization layer, said second removable layers being located over said first and second integrated circuit chips and in said area interposed between said first and second chips, said interposed area dividing the portion of said substrate carrying said first and second integrated circuit chips into first and second regions, respectively, said second removable layers covering only portions of said first layer of metallization, said first region being maintained at said first voltage level and said second region being maintained at said second voltage level; electroplating a second layer of metallization on top of said first layer of metallization at locations where said first layer of metallization is exposed; stripping said second removable layers of protecting material; etching said first layer of metallization at locations where said first layer of metallization has been exposed by the step of stripping said second removable layers of protecting material; and stripping said first removable layers of protecting material.
Claim 13
Independent Claim
285 words
A method of connecting a first voltage level to a first integrated circuit chip and a second voltage level to a second integrated circuit chip wherein either voltage level may be ground, said first and second integrated circuit chips being affixed to a common substrate, said method comprising the steps of: affixing said first and second integrated circuit chips to said substrate with a nonconductive adhesive; protecting electrically active areas of said first and second integrated circuit chips and an area interposed therebetween on said substrate by applying first removable layers of protecting material over said areas; coating with a first metallization layer said first and second integrated circuit chips, said first removable layers of protecting material, and said common substrate; applying second removable layers of protecting material over said first metallization layer, said second removable layers being located over said first and second integrated circuit chips and in said area interposed between said first and second chips, said interposed area dividing the portion of said substrate carrying said first and second integrated circuit chips into first and second regions, respectively, said second removable layers covering only portions of said first layer of metallization, said first region being maintained at said first voltage level and said second region being maintained at said second voltage level; electroplating a second layer of metallization on top of said first layer of metallization at locations where said first layer of metallization is exposed; stripping said second removable layers of protecting material; etching said first layer of metallization at locations where said first layer of metallization has been exposed by the step of stripping said second removable layers of protecting material; and stripping said first removable layers of protecting material.
Claim 14
Dependent Claim
16 words
The method of claim 11 wherein said second removable layers are comprised of a negative resist.
Claim 15
Dependent Claim
16 words
The method of claim 11 wherein said second removable layers are comprised of a positive resist.
Claim 16
Dependent Claim
21 words
The method of claim 11 wherein the difference between said first and second voltage levels may range up to 30 volts.
Claim 17
Dependent Claim
15 words
The method of claim 11 wherein said first removable layers are comprised of a photoresist.
Claim 18
Dependent Claim
15 words
The method of claim 11 wherein said first removable layers are comprised of a polyimide.
References Cited (Backward Citations)
US4783695A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-27 | 1994-11-26 | 1995-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-27 | 1998-11-26 | 1999-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-27 | 2002-11-26 | 2003-05-28 | $7700.00 | Window Closed / Lapsed |