US5018256A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Architecture and process for integrating DMD with control circuit substrates
Assignee: Texas Instruments Inc
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Filing: 1990-06-29
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Granted: 1991-05-28
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Expires: 2010-06-29
Abstract
Abstract DMD projection light values for HDTV have various manufacturing requirements, including the high yield integration of the DMD superstructure on top of an underlying CMOS address circuit. The CMOS chip surface contains several processing artifacts that can lead to reduced yield for the DMD superstructure. A modified DMD architecture and process are disclosed that minimizes the yield losses caused by these CMOS artifacts while also reducing parasitic coupling of the high voltage reset pulses to the underlying CMOS address circuitry.
Inventors
- 👤 Larry J. Hornbeck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:31
CPC Classifications
G; G02; G02B; G02B26/00; G02B26/08; G02B26/0816; G02B26/0833; G02B26/0841; H; H10; H10P; H10P52/00; H10P14/00; H10P14/60; H10P14/68; H10P14/683; Y; Y02; Y02P; Y02P80/00; Y02P80/30
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
119 words
A method of planarizing an integrated semiconductor substrate for the purpose of constructing thereon an electromechanical device, said method comprising the steps of: spinning on a first spacer consisting of a planarizing liquid organic material covering said substrate; patterning and curing said first spacer to form first support posts electrodes of said electromechanical device; forming said electrodes over said first spacer; spinning on a second spacer consisting of a planarizing liquid organic material covering said electrodes; patterning and curing said second spacer to form second support posts for the mechanical portion of said electromechanical device; establishing on a said second spacer a plurality of mechanical elements supported by said second support posts; and removing said first and second spacers.
Claim 2
Independent Claim
119 words
A method of planarizing an integrated semiconductor substrate for the purpose of constructing thereon an electromechanical device, said method comprising the steps of: spinning on a first spacer consisting of a planarizing liquid organic material covering said substrate; patterning and curing said first spacer to form first support posts electrodes of said electromechanical device; forming said electrodes over said first spacer; spinning on a second spacer consisting of a planarizing liquid organic material covering said electrodes; patterning and curing said second spacer to form second support posts for the mechanical portion of said electromechanical device; establishing on a said second spacer a plurality of mechanical elements supported by said second support posts; and removing said first and second spacers.
Claim 3
Dependent Claim
41 words
The method set forth in claim 1 wherein said removing step allows mechanical gaps to exist between certain portions of said integrated semi-conductor substrate and said formed electrodes and between certain portions of said formed electrodes and said established mechanical elements.
Claim 4
Dependent Claim
30 words
The method set forth in claim 2 wherein said substrate is a CMOS substrate having a traditional oxide or nitride protective top coating over which said planarizing liquid is spun-on.
Claim 5
Independent Claim
137 words
The method of planarizing an existing CMOS substrate containing integrated circuits and formed having a traditional protective oxide or nitride top covering and wherein said existing substrate top covering contains hillocks, pin holes, or steep sidewall contact areas, the method comprising the steps of: spinning-on a planarizing material covering said top covering; patterning said planarizing material to allow for the formation of support posts in physical contact with said top covering; curing said planarizing material to withstand a first certain temperature; forming on top of said cured planarizing material a first mechanical structure containing support posts in physical contact with said top covering; and removing said cured planarizing material to leave a mechanical gap between said top covering and said formed first mechanical structure, except where said support posts of said mechanical structure contact said top covering.
Claim 6
Independent Claim
137 words
The method of planarizing an existing CMOS substrate containing integrated circuits and formed having a traditional protective oxide or nitride top covering and wherein said existing substrate top covering contains hillocks, pin holes, or steep sidewall contact areas, the method comprising the steps of: spinning-on a planarizing material covering said top covering; patterning said planarizing material to allow for the formation of support posts in physical contact with said top covering; curing said planarizing material to withstand a first certain temperature; forming on top of said cured planarizing material a first mechanical structure containing support posts in physical contact with said top covering; and removing said cured planarizing material to leave a mechanical gap between said top covering and said formed first mechanical structure, except where said support posts of said mechanical structure contact said top covering.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-05-27 | 1994-11-26 | 1995-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-27 | 1998-11-26 | 1999-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-27 | 2002-11-26 | 2003-05-28 | $7700.00 | Window Closed / Lapsed |