Dual rail dilated switching networks

Claim 3

The method of claim 1 further comprising a step of developing a set of control signals, said set comprising a pair of control signals for each of said dual rail switches, with each pair of control signals developed for a dual rail switch arranged to insure that no more than one of active signals applied to said dual rail switch is routed to each of said output pairs of leads of said dual rail switch.

Claim 4

A network for routing signals comprising: a plurality of dual rail routing elements, each comprising a first pair of input leads, a second pair of input leads, a first pair of output leads and a second pairs of output leads; a first interconnection arrangement wherein said first pair of input leads of one of said dual rail routing elements is connected to a pair of output leads of another one of said dual rail routing elements, and said second pair of input leads of said one of said dual rail routing elements is connected to a pair of output leads of still another one of said dual rail routing elements; a plurality of single rail routing elements, each comprising one pair of input leads and one pair of output leads; a second interconnection arrangement wherein said input leads of one of said single rail routing elements are connected to output leads of different ones of said single rail routing elements; and a combiner element interposed between each output pair of leads of dual rail switch that communicates the output signal of said output pair of leads to a single rail switch, with said combiner element having two inputs and one output.

Claim 5

A network for routing signals comprising: a plurality of dual rail routing elements, each comprising a first pair of input leads, a second pair of input leads, a first pair of output leads and a second pairs of output leads; a first interconnection arrangement wherein said first pair of input leads of one of said dual rail routing elements is connected to a pair of output leads of another one of said dual rail routing elements, and said second pair of input leads of said one of said dual rail routing elements is connected to a pair of output leads of still another one of said dual rail routing elements; a plurality of single rail routing elements, each comprising one pair of input leads and one pair of output leads; a second interconnection arrangement wherein said input leads of one of said single rail routing elements are connected to output leads of different ones of said single rail routing elements; and a combiner element interposed between each output pair of leads of dual rail switch that communicates the output signal of said output pair of leads to a single rail switch, with said combiner element having two inputs and one output.

Claim 6

The network of claim 3, wherein said combiner element performs a logical OR function.

Claim 7

the network of claim 3 wherein said combiner element performs a selection function.

Claim 8

A dilated omega network comprising a plurality of interconnected stages, where each stage comprises N 2×2 switches that include 2 input links and two output links each, N being an integer, the interconnection of said stage comprising links that connect switches in stage i to switches in stage i+1, where i is an integer, in accordance with the pattern O(p l p 1-1 p 1-2 . . . p j . . . p 2 p 1 p 0 ) i → I(p l-1 p N-2 . . . p j . . . p 2 p 1 p 1 p 0 ) i+1 , where l is an integer such that N≦2 1 , p k represents the k+1 bit in a binary representation of a designation of a link of a switch, where such designation is an integer in the range 0 to 2N and is twice the value of the designation of the switch, and O(p l p l-1 p l-2 . . . p j . . . p 2 p 1 p 0 ) i designates output link (p l p l-1 p l-2 . . . p j . . . p 2 p 1 p 0 ) at stage i while I(p l-1 p l-2 . . . p j . . . p 2 p 1 p 1 p 0 ) i+1 designates input link (p l-1 p l-2 . . . p j . . . p 2 p 1 p 1 p 0 ) at stage i+1.

Claim 9

A dilated omega network comprising a plurality of interconnected stages, where each stage comprises N 2×2 switches that include 2 input links and two output links each, N being an integer, the interconnection of said stage comprising links that connect switches in stage i to switches in stage i+1, where i is an integer, in accordance with the pattern O(p l p 1-1 p 1-2 . . . p j . . . p 2 p 1 p 0 ) i → I(p l-1 p N-2 . . . p j . . . p 2 p 1 p 1 p 0 ) i+1 , where l is an integer such that N≦2 1 , p k represents the k+1 bit in a binary representation of a designation of a link of a switch, where such designation is an integer in the range 0 to 2N and is twice the value of the designation of the switch, and O(p l p l-1 p l-2 . . . p j . . . p 2 p 1 p 0 ) i designates output link (p l p l-1 p l-2 . . . p j . . . p 2 p 1 p 0 ) at stage i while I(p l-1 p l-2 . . . p j . . . p 2 p 1 p 1 p 0 ) i+1 designates input link (p l-1 p l-2 . . . p j . . . p 2 p 1 p 1 p 0 ) at stage i+1.

Claim 10

A dilated diamond array comprising a plurality of interconnected stages, where each stage comprises 2×2 switches that include 2 input links and two output links each, the interconnection of said stage comprising links that connect switches in stage i to switches in stage i+1, where i is an integer, in accordnace with the pattern (1) O(8n+j) i for j=0,1,2,3→I(8n+j-2) i for all non-negative 8n+j-2, where n is an integer, O(8n+j) i designates output link 8n+j in stage i and; I(8n+j-2) i designates input link 8n+j-2 in stage i; (2) O(8n+j) i for j=4,5→I(8n+j-2) i+1 where I(8n+j-2) i+1 designates input link 8n+j-2 in stage i+1; and (3) (8n+j) i for j=6,7→I(8n+j+2) i+1 where I(8n+j+2) i+1 designates input link 8n+j+2 in stage i+1.

Claim 11

A dilated diamond array comprising a plurality of interconnected stages, where each stage comprises 2×2 switches that include 2 input links and two output links each, the interconnection of said stage comprising links that connect switches in stage i to switches in stage i+1, where i is an integer, in accordnace with the pattern (1) O(8n+j) i for j=0,1,2,3→I(8n+j-2) i for all non-negative 8n+j-2, where n is an integer, O(8n+j) i designates output link 8n+j in stage i and; I(8n+j-2) i designates input link 8n+j-2 in stage i; (2) O(8n+j) i for j=4,5→I(8n+j-2) i+1 where I(8n+j-2) i+1 designates input link 8n+j-2 in stage i+1; and (3) (8n+j) i for j=6,7→I(8n+j+2) i+1 where I(8n+j+2) i+1 designates input link 8n+j+2 in stage i+1.

Claim 12

A dilated banyan network comprising a plurality of interconnected stages, where each stage comprises N 2×2 switches that include 2 input links and two output links each, N being an integer, the interconnection of said stage comprising links that connect switches in stage i to switches in stage i+1, where i is an integer, in accordnace with the pattern O(p l p l-1 . . . p j+2 p j+1 . . . p l p 0 ) i →I(p l p l-1 . . . p j+2 p 0 . . . p l p j+1 ) i+1 . where 1 is an integer such that N≦2 1 , p k represents the k+1 bit in a binary representation of a designation of a link of a switch, where such designation is an integer in the range 0 to 2N and is twice the value of the designation of the switch, and O(p l p l-1 . . . p j+2 p j+1 . . . p l p 0 ) i designates output link (p l p l-1 . . . p j+2 p j+1 . . . p l p 0 ) at stage i while I(p l p l-1 . . . p j+2 p 0 . . . p l p j+1 ) i+1 designates input link (p l p l-1 . . . p j+2 p 0 . . . p l p j+1 ) stage i+1.

Claim 13

A dilated banyan network comprising a plurality of interconnected stages, where each stage comprises N 2×2 switches that include 2 input links and two output links each, N being an integer, the interconnection of said stage comprising links that connect switches in stage i to switches in stage i+1, where i is an integer, in accordnace with the pattern O(p l p l-1 . . . p j+2 p j+1 . . . p l p 0 ) i →I(p l p l-1 . . . p j+2 p 0 . . . p l p j+1 ) i+1 . where 1 is an integer such that N≦2 1 , p k represents the k+1 bit in a binary representation of a designation of a link of a switch, where such designation is an integer in the range 0 to 2N and is twice the value of the designation of the switch, and O(p l p l-1 . . . p j+2 p j+1 . . . p l p 0 ) i designates output link (p l p l-1 . . . p j+2 p j+1 . . . p l p 0 ) at stage i while I(p l p l-1 . . . p j+2 p 0 . . . p l p j+1 ) i+1 designates input link (p l p l-1 . . . p j+2 p 0 . . . p l p j+1 ) stage i+1.