US5017811A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS TTL input buffer using a ratioed inverter with a threshold voltage adjusted N channel field effect transistor
Assignee: Conexant Systems LLC
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Filing: 1989-10-27
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Granted: 1991-05-21
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Expires: 2009-10-27
Abstract
Abstract The invention applies a weak forward bias to the body of the NFET transistor of a PFET-NFET TTL inverter buffer circuit to lower the NFET threshold voltage by about 0.45 volts, as a result of 1.5μ amps of body-source current providing a body to source voltage of about 0.5 volts to achieve a near ideal switch point of 1.45 volts under nominal conditions. Also a modified inverter circuit with biasing source, two diodes for trip voltage of 1.4 volts and a comparator constitute a central bias generator for supplying proper bias to the body of the NFETs of a plurality of TTL input buffers.
Inventors
- 👤 Eugene R. Worley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:51
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/003; H03K19/00369; H03K19/00384; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
56 words
A TTL level input receiver, comprising in combination: a ratioed inverter comprising a series connected CMOS PFET and CMOS NFET for receiving a TTL level input and outputting a CMOS level output; and, biasing means connected to the body of the NFET to apply a forward bias current for lowering the threshold voltage of the NFET.
Claim 2
Dependent Claim
56 words
A TTL level input receiver, comprising in combination: a ratioed inverter comprising a series connected CMOS PFET and CMOS NFET for receiving a TTL level input and outputting a CMOS level output; and, biasing means connected to the body of the NFET to apply a forward bias current for lowering the threshold voltage of the NFET.
Claim 3
Dependent Claim
93 words
A TTL level input receiver, comprising in combination: a ratioed inverter comprising a series connected CMOS PFET and CMOS NFET for receiving a TTL level input and outputting a CMOS level output; biasing means connected to the body of the NFET to apply a forward bias current for lowering the threshold voltage of the NFET; the PFET is connected as a pull up device and the NFET is connected as a pull down device; and, said biasing means comprises a CMOS PFET having a width to length ratio of the order of 4:350.
Claim 4
Dependent Claim
93 words
A TTL level input receiver, comprising in combination: a ratioed inverter comprising a series connected CMOS PFET and CMOS NFET for receiving a TTL level input and outputting a CMOS level output; biasing means connected to the body of the NFET to apply a forward bias current for lowering the threshold voltage of the NFET; the PFET is connected as a pull up device and the NFET is connected as a pull down device; and, said biasing means comprises a CMOS PFET having a width to length ratio of the order of 4:350.
Claim 5
Dependent Claim
24 words
The receiver of claim 2, further comprising a bypass capacitor connected to suppress gate bumping of the body voltage via gate to body capacitance.
Claim 6
Dependent Claim
95 words
A TTL level input receiver, comprising in combination: an inverter comprising a CMOS PFET and a CMOS NFET connected in series between a first source of potential and a second source of potential; the gates of the PFET and NFET connected to receive a TTL level input; the drain of the PFET connected to the drain of the NFET to provide a CMOS level output; and, biasing means connected between the first source of potential and the body of the NFET to apply a forward bias current for lowering the threshold voltage of the NFET.
Claim 7
Dependent Claim
95 words
A TTL level input receiver, comprising in combination: an inverter comprising a CMOS PFET and a CMOS NFET connected in series between a first source of potential and a second source of potential; the gates of the PFET and NFET connected to receive a TTL level input; the drain of the PFET connected to the drain of the NFET to provide a CMOS level output; and, biasing means connected between the first source of potential and the body of the NFET to apply a forward bias current for lowering the threshold voltage of the NFET.
Claim 8
Dependent Claim
126 words
A ratioed inverter biasing apparatus used to bias the NFET bodies of one or more TTL level input receivers, comprising in combination: a sacrificial ratioed inverter comprising a series connected CMOS PFET and CMOS NFET having their gates connected together and the drain of the NFET connected to the drain of the PFET; biasing means connected to the body of the NFET to apply a forward bias current for lowering the threshold voltage of the NFET; said biasing means comprising a two lead input comparator having a first lead input providing 1.4 volts and a second lead input connected to the gates and the connected together PFET drain and NFET drain; and said comparator having an output to serve as a biasing supply for said receivers.
Claim 9
Dependent Claim
126 words
A ratioed inverter biasing apparatus used to bias the NFET bodies of one or more TTL level input receivers, comprising in combination: a sacrificial ratioed inverter comprising a series connected CMOS PFET and CMOS NFET having their gates connected together and the drain of the NFET connected to the drain of the PFET; biasing means connected to the body of the NFET to apply a forward bias current for lowering the threshold voltage of the NFET; said biasing means comprising a two lead input comparator having a first lead input providing 1.4 volts and a second lead input connected to the gates and the connected together PFET drain and NFET drain; and said comparator having an output to serve as a biasing supply for said receivers.
Claim 10
Dependent Claim
132 words
A central bias generator for at least one TTL level input receiver, comprising in combination: an inverter comprising a CMOS PFET and a CMOS NFET connected in series between a first source of potential and a second source of potential; the gates of the PFET and NFET connected together; the drain of the PFET connected to the drain of the NFET; a comparator; biasing means connected between the first source of potential and the body of the NFET via the comparator to apply a forward bias current for lowering the threshold voltage of the NFET; said comparator further connected to said gates and drains; a pair of series connected diodes connected between the second source of potential and the comparator to provide a 1.4 volt output from the comparator for said receivers.
Claim 11
Dependent Claim
132 words
A central bias generator for at least one TTL level input receiver, comprising in combination: an inverter comprising a CMOS PFET and a CMOS NFET connected in series between a first source of potential and a second source of potential; the gates of the PFET and NFET connected together; the drain of the PFET connected to the drain of the NFET; a comparator; biasing means connected between the first source of potential and the body of the NFET via the comparator to apply a forward bias current for lowering the threshold voltage of the NFET; said comparator further connected to said gates and drains; a pair of series connected diodes connected between the second source of potential and the comparator to provide a 1.4 volt output from the comparator for said receivers.
Claim 12
Dependent Claim
33 words
The generator of claim 6, further comprising: a bypass capacitor connected between the comparator and the second source of potential to suppress gate bumping of the body biasing via gate to body capacitance.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-20 | 1994-11-19 | 1995-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-20 | 1998-11-19 | 1999-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-20 | 2002-11-19 | 2003-05-21 | $7700.00 | Window Closed / Lapsed |